Patents Examined by Yosef Gebreyesus
  • Patent number: 10510875
    Abstract: A method includes forming a fin structure on the substrate, wherein the fin structure includes a first fin active region; a second fin active region; and an isolation feature separating the first and second fin active regions; forming a first gate stack on the first fin active region and a second gate stack on the second fin active region; performing a first recessing process to a first source/drain region of the first fin active region by a first dry etch; performing a first epitaxial growth to form a first source/drain feature on the first source/drain region; performing a fin sidewall pull back (FSWPB) process to remove a dielectric layer on the second fin active region; and performing a second epitaxial growth to form a second source/drain feature on a second source/drain region of the second fin active region.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chih-Teng Liao, Chih-Shan Chen, Yi-Wei Chiu, Chih Hsuan Cheng, Tzu-Chan Weng
  • Patent number: 10505029
    Abstract: A semiconductor device including an IE-type trench gate IGBT requires to be improved in IE effect to reduce on voltage. The semiconductor device includes a trench gate electrode or a trench emitter electrode between an active cell region and an inactive cell region. The trench gate electrode and the trench emitter electrode are provided across the inactive cell region.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: December 10, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Nao Nagata
  • Patent number: 10504936
    Abstract: A stretchable display device includes: a first pixel substrate includes a first body part and a first hinge part connected to the first body part; a second pixel substrate includes a second body part and a second hinge part connected to the second body part. A second direction neighboring cutout pattern is disposed between the first hinge part connected to the first body part and the second hinge part connected to the second body part; a first power line disposed at the first hinge part connected to the first body part and a second power line disposed at a second hinge part is connected to the second body part. The first power line and second power line are disposed at substantially equal distances in the first direction based on a reference line extending in correspondence to the second direction neighboring cutout pattern.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: December 10, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Gyung Soon Park, Il-Joo Kim, Jun Ki Jeong
  • Patent number: 10504884
    Abstract: In an aspect, a circuit can include drain and source terminals; a HEMT having a drain and a source, wherein the drain is coupled to the drain terminal; and a variable resistor having a first electrode and a second electrode. The first electrode can be coupled to the source of the HEMT, and the second electrode can be coupled to the source terminal. In another aspect, an electronic device can include a source terminal; a heterojunction between a channel layer and a barrier layer; a source electrode of a HEMT overlying the channel layer; a first resistor electrode overlying the channel layer and spaced apart from the source electrode, wherein the first resistor electrode is coupled to the source terminal; and a variable resistor, wherein from a top view, the variable resistor is disposed along the heterojunction between the source electrode and the first resistor electrode.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: December 10, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume Roig-Guitart, Aurore Constant
  • Patent number: 10506706
    Abstract: A printed circuit board can include a base layer, a first surface and a second surface opposite to each other. A first routing layer can be on the first surface and a second routing layer can be on the second surface, the first routing layer can be provided at an upper part of each of the first and second regions and the second routing layer can be provided at a lower part of each of the first and second regions. The upper part of the first region can have a first line-area ratio, the upper part of the second region can have a second line-area ratio, the lower part of the first region can have a third line-area ratio, the lower part of the second region can have a fourth line-area ratio, the second and third line-area ratios can be greater than each of the first and fourth line-area ratios.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: December 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shle-Ge Lee, Youngbae Kim
  • Patent number: 10472227
    Abstract: A micro-device comprising: a substrate, a stationary element rigidly connected to the substrate, a first mobile element suspended from the stationary element by first retention elements and configured to move with respect to the stationary element, a second mobile element suspended from the first mobile element by second retention elements and configured to move with respect to the first mobile element and the stationary element, a first cavity, at least some of the walls of which are formed by the stationary element and in which the first mobile element is encapsulated, a second cavity positioned in the first cavity, at least some of the walls of which are formed by the first mobile element, in which the second mobile element is encapsulated and which is insulated from the first cavity.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: November 12, 2019
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, SAFRAN
    Inventors: Audrey Berthelot, Mikael Colin
  • Patent number: 10475716
    Abstract: The sensor semiconductor device comprises a substrate (1) with a main surface (2), a sensor region (3) on or above the main surface, a coating layer (4) above the main surface, and a trench (5) formed in the coating layer around the sensor region. The trench provides drainage of a liquid from the coating layer.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: November 12, 2019
    Assignee: ams AG
    Inventors: Nebojsa Nenadovic, Agata Sakic, Micha In't Zandt, Frederik Willem Maurits Vanhelmont, Hilco Suy, Roel Daamen
  • Patent number: 10475897
    Abstract: In a method of forming a Group III-V semiconductor layer on a Si substrate, a first source gas containing a Group V element is supplied to a surface of the Si substrate while heating the substrate at a first temperature, thereby terminating the Si surface with the Group V element. Then, a second source gas containing a Group III element is supplied to the surface while heating the substrate at a second temperature, thereby forming a nucleation layer directly on the surface of the Si substrate. After the nucleation layer is formed, the supply of the second source gas is stopped and the substrate is annealed at a third temperature while the first source gas being supplied, thereby foaming a seed layer. After the annealing, the second source gas is supplied while heating the substrate at a fourth temperature, thereby forming a body III-V layer semiconductor on the seed layer.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: November 12, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Mark Van Dal, Matthias Passlack, Martin Christopher Holland
  • Patent number: 10468171
    Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a magnetic tunnel junction stack. The magnetic tunnel junction stack includes a seed layer, first and second pinned layers, and a coupling layer. The seed layer includes holmium. The first pinned layer overlies the seed layer, where the first pinned layer is magnetic, and the non-magnetic coupling layer overlies the first pinned layer. The second pinned layer overlies the coupling layer, where the second pinned layer is also magnetic.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: November 5, 2019
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wai Cheung Law, Taiebeh Tahmasebi, Dimitri Houssameddine, Michael Nicolas Albert Tran, Chim Seng Seet, Kai Hung Alex See, Wen Siang Lew
  • Patent number: 10468337
    Abstract: A package for an electronic component includes a housing and a leadframe embedded in the housing. The leadframe includes a first section, a second section and a third section which are electrically isolated from one another. The first section and the second section each include an L-shape.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: November 5, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Sok Gek Beh, Siew Lee Yeoh, Wing Yew Wong
  • Patent number: 10468365
    Abstract: In a method for manufacturing a radiation detector, counter pixel electrodes 33 are formed on a counter substrate 2 at positions facing a plurality of pixel electrodes formed on a signal reading substrate, and wall bump electrodes 34 are further formed on the counter pixel electrodes 33. In order to achieve the above, a resist R is applied, and the resist R is exposed to light to form openings O. When Au sputter deposition is performed on the openings O, only some of the Au is deposited on the bottom surface in the openings O as the counter pixel electrodes 33. The rest of the Au is not deposited on the bottom surface in the openings O, and the most of the remaining Au adheres to the inner walls of the openings O to form wall bump electrodes 34. The bump electrodes 34 are cylindrical, making it possible to reduce the pressure acting on the signal reading substrate by an extent corresponding to the decrease in the bonding area in comparison to conventional bump-shaped bump electrodes.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: November 5, 2019
    Assignees: SHIMADZU CORPORATION, TOHOKU-MICROTEC CO., LTD.
    Inventors: Hiroyuki Kishihara, Toshinori Yoshimuta, Satoshi Tokuda, Yukihisa Wada, Makoto Motoyoshi
  • Patent number: 10468355
    Abstract: A method includes forming a metal post over a first dielectric layer, attaching a second dielectric layer over the first dielectric layer, encapsulating a device die, the second dielectric layer, a shielding structure, and the metal post in an encapsulating material, planarizing the encapsulating material to reveal the device die, the shielding structure, and the metal post, and forming an antenna electrically coupling to the device die. The antenna has a portion vertically aligned to a portion of the device die.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kai-Chiang Wu, Chen-Hua Yu, Ching-Feng Yang, Meng-Tse Chen
  • Patent number: 10453868
    Abstract: A display apparatus includes a substrate, a gate line disposed on the substrate and extending along a first direction, a gate insulating layer covering the gate line, a first data line disposed on the gate insulating layer and extending along a second direction different from the first direction, a first insulating layer covering the first data line, and a second data line disposed between the substrate and the gate insulating layer, or disposed on the first insulating layer, wherein the second data line extends along the second direction, and both of the first data line and the second data line intersect with the gate line.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: October 22, 2019
    Assignee: INNOLUX CORPORATION
    Inventor: Toshiya Inada
  • Patent number: 10453960
    Abstract: Field-effect transistor, the source and drain regions whereof are formed from a crystalline structure comprising: a first layer comprising two main faces parallel to one another and two lateral faces parallel to one another, the main faces being perpendicular to the lateral faces, a second layer overlapping the first layer, the second layer comprising a first main face and a second main face parallel to one another and two lateral faces, the first main face being in contact with the first layer, the lateral faces forming an angle ? in the range 50° to 59°, and preferably a 53° angle, with the first main face.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: October 22, 2019
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Vincent Mazzocchi, Laurent Grenouillet
  • Patent number: 10453821
    Abstract: A connection system of semiconductor packages includes: a printed circuit board having a first surface, and a second surface, opposing the first surface; a first semiconductor package disposed on the first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures; and a second semiconductor package disposed on the second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures. The first semiconductor package includes an application processor (AP) and a power management integrated circuit (PMIC) disposed side by side, and the second semiconductor package includes a memory.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yun Tae Lee, Han Kim, Hyung Joon Kim
  • Patent number: 10454023
    Abstract: A spin current magnetization rotational element includes: a ferromagnetic metal layer; a spin-orbit torque wiring configured to extend in a first direction perpendicular to a lamination direction of the ferromagnetic metal layer and formed on one surface of the ferromagnetic metal layer; and a ferromagnetic electrode layer formed outside the ferromagnetic metal layer on any of surfaces of the spin-orbit torque wiring in a top view from the lamination direction. A direction of magnetization of the ferromagnetic metal layer is changeable by spin-orbit torque generated by a spin-orbit interaction in the spin-orbit torque wiring and an influence of spin diffused from the ferromagnetic electrode layer.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: October 22, 2019
    Assignee: TDK CORPORATION
    Inventors: Zhenyao Tang, Yohei Shiokawa, Tomoyuki Sasaki
  • Patent number: 10446400
    Abstract: A method provides a gate structure for a plurality of components of a semiconductor device. A silicate layer is provided. In one aspect, the silicate layer is provided on a channel of a CMOS device. A high dielectric constant layer is provided on the silicate layer. The method also includes providing a work function metal layer on the high dielectric constant layer. A low temperature anneal is performed after the high dielectric constant layer is provided. A contact metal layer is provided on the work function metal layer.
    Type: Grant
    Filed: February 16, 2018
    Date of Patent: October 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wei-E Wang, Mark S. Rodder, Borna J. Obradovic
  • Patent number: 10431720
    Abstract: A light emitting device includes: a light emitting element including: a semiconductor structure including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer, each containing a nitride semiconductor, a p-electrode disposed on a portion of a surface of the p-type semiconductor layer on a side opposite to a surface provided with the active layer, and an n-electrode disposed on a surface of the n-type semiconductor layer on a side opposite to a surface provided with the active layer in a region other than a region facing the p-electrode; and a protective film continuously covering a surface of the n-electrode and a surface of the n-type semiconductor layer. The protective film includes a first metal oxide film and a second metal oxide film that are alternately layered, the first metal oxide film containing a first metal, and the second metal oxide film containing a second metal.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: October 1, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Takaaki Tada, Takayoshi Wakaki
  • Patent number: 10347552
    Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: July 9, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Ryuichi Oikawa, Toshihiko Ochiai, Shuuichi Kariyazaki, Yuji Kayashima, Tsuyoshi Kida
  • Patent number: 10347513
    Abstract: Embodiments are related to systems and methods for fluidic assembly, and more particularly to systems and methods for assuring deposition of elements in relation to a substrate.
    Type: Grant
    Filed: January 1, 2018
    Date of Patent: July 9, 2019
    Assignee: eLux Inc.
    Inventors: Paul John Schuele, David Robert Heine, Mark Albert Crowder, Sean Mathew Garner, Changqing Zhan, Avinash Tukaram Shinde, Kenji Alexander Sasaki, Kurt Michael Ulmer