Abstract: A method and system for changing a pressure within at least one enclosure in a MEMS device are disclosed. In a first aspect, the method comprises applying a laser through one of the at least two substrates onto a material which changes the pressure within at least one enclosure when exposed to the laser, wherein the at least one enclosure is formed by the at least two substrates. In a second aspect, the system comprises a MEMS device that includes a first substrate, a second substrate bonded to the first substrate, wherein at least one enclosure is located between the first and the second substrates, a metal layer within one of the first substrate and the second substrate, and a material vertically oriented over the metal layer, wherein when the material is heated the material changes a pressure within the at least one enclosure.

Abstract: A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns; and a contact on at least one side of the gate electrode, the contact contacting the first fin pattern, the contact having a bottom surface that does not contact the second fin pattern, a height from a bottom of the first trench to a topmost end of the first fin pattern in a region in which the contact intersects the first fin pattern being a first height, and a height from the bottom of the first trench to a topmost end of the second fin pattern in a region in which an extension line of the contact extending along a direction in which the gate electrode extends intersects the second fin pattern being a second height, the first height being smaller than the second height.

Abstract: The present disclosure relates to an integrated circuit, which includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a lower metal layer, an intermediate metal layer disposed over the lower metal layer, and an upper metal layer disposed over the intermediate metal layer. An upper surface of the lower metal layer and a lower surface of the intermediate metal layer are spaced vertically apart by a first distance. A resistive random access memory (RRAM) cell is arranged between the lower metal layer and the upper metal layer. The RRAM cell includes a bottom electrode and a top electrode which are separated by a data storage layer having a variable resistance. The data storage layer vertically spans a second distance that is greater than the first distance.

Abstract: Die (110) and/or undiced wafers and/or multichip modules (MCMs) are attached on top of an interposer (120) or some other structure (e.g. another integrated circuit) and are covered by an encapsulant (160). Then the interposer is thinned from below. Before encapsulation, a layer (410) more rigid than the encapsulant is formed on the interposer around the die to reduce or eliminate interposer dishing between the die when the interposer is thinned by a mechanical process (e.g. CMP). Other features are also provided.

Abstract: A method comprises forming one or more fins in a first region on an insulated substrate. The method also comprises forming one or more fins formed in a second region on the insulated substrate. The insulated substrate comprising a silicon substrate, and an insulator layer deposited on the silicon substrate. The one or more fins in the first region comprising a first material layer deposited on the insulator layer. The one or more fins in the second region comprising a second material layer deposited on the insulator layer.

Abstract: A phosphor composition is disclosed. A phosphor composition, comprises at least 10 atomic % bromine; silicon, germanium or combination thereof; oxygen; a metal M, wherein M comprises zinc (Zn), magnesium (Mg), calcium (Ca), strontium (Sr), barium (Ba), or combinations thereof; and an activator comprising europium. The phosphor composition is formed from combining carbonate or oxides of metal M, silicon oxide, and europium oxide; and then firing the combination. A lighting apparatus including the phosphor composition is also provided. The phosphor composition may be combined with an additional phosphor to generate white light.

Abstract: A horizontal multilayer junction-edge field emitter includes a plurality of vertically-stacked multilayer structures separated by isolation layers. Each multilayer structure is configured to produce a 2-dimensional electron gas at a junction between two layers within the structure. The emitter also includes an exposed surface intersecting the 2-dimensional electron gas of each of the plurality of vertically-stacked multilayer structures to form a plurality of effectively one-dimensional horizontal line sources of electron emission.

Abstract: A method of an aspect includes forming a first thicker layer of a first material over a first region having a first surface material by separately forming each of a first plurality of thinner layers by selective chemical reaction. The method also includes limiting encroachment of each of the first plurality of thinner layers over a second region that is adjacent to the first region. A second thicker layer of a second material is formed over the second region having a second surface material that is different than the first surface material.

Abstract: Embodiments of the present disclosure generally relate to a semiconductor device including layers of group III-V semiconductor materials. In one embodiment, the semiconductor device includes a phosphorous containing layer deposited on a silicon substrate, wherein a lattice mismatch between the phosphorous containing layer and the silicon substrate is less than 5%, a group III-V compound nucleation layer deposited on the phosphorous containing layer at a first temperature, the group III-V compound nucleation layer having a first thickness, a group III-V compound transition layer deposited on the group III-V compound nucleation layer at a second temperature higher than the first temperature, the group III-V compound transition layer having a second thickness larger than the first thickness, and the group III-V compound nucleation layer is different from the group III-V compound transition layer, and an active layer deposited on the group III-V compound transition layer.

Abstract: Provided is a metal oxide film, including a component having a peak position, in an XPS spectrum thereof, within a range corresponding to a binding energy of from 402 eV to 405 eV, the metal oxide film satisfying a relationship represented by Equation (1): A/(A+B)?0.39, when an intensity of peak energy attributed to nitrogen 1s electron is obtained by peak separation, and a manufacturing method of the same, an oxide semiconductor film, a thin-film transistor, a display apparatus, an image sensor, and an X-ray sensor. In Equation (1), A represents a peak area of the component having a peak position within a range corresponding to a binding energy of from 402 eV to 405 eV, and B represents a peak area of a component having a peak position within a range corresponding to a binding energy of from 406 eV to 408 eV.

Abstract: The present disclosure provides an array substrate, a method for producing the same, a display panel and a display apparatus. The array substrate comprises: a glass substrate; a flexible substrate comprising a first region and a second region, the glass substrate being supported on a lower surface of the first region of the flexible substrate and the second region projecting from the first region towards the external of the glass substrate; a display array formed on the first region of the flexible substrate; and a peripheral circuit formed on the second region of the flexible substrate. The array substrate can achieve a display apparatus with super narrow frame, even without frame.

Abstract: An area of a region arranged on one side out of a display region in a direction in which scanning signal lines extend is reduced. A display apparatus includes: a partial circuit; a plurality of scanning signal lines; and a plurality of scanning signal connection wirings for connecting the partial circuit and each of the plurality of scanning signal lines. Each of the plurality of scanning signal lines extends in an X-axis direction, and is arranged with a pitch in a Y-axis direction. A plurality of ends respectively included in the plurality of scanning signal connection wirings are connected to the partial circuit, and are arranged in the Y-axis direction. A distance in the Y-axis direction between the respective centers of the two ends adjacent to each other is narrower than the pitch.

Abstract: A semiconductor device includes a semiconductor chip, a bump electrode, a molding portion, a redistribution layer and an outer connection electrode. The bump electrode is provided on an upper face of the semiconductor chip. The molding portion encapsulates an entire side face of the semiconductor chip and seals the bump electrode so that a part of the bump electrode is exposed. The redistribution layer is provided on an upper face of the molding portion and is electrically coupled to the semiconductor chip via the bump electrode. The outer connection electrode is provided on an upper face of the redistribution layer and is electrically coupled to the bump electrode via the redistribution layer.

Abstract: Provided is a peep prevention display, wherein a peep prevention film layer is provided on the light exit side of the peep prevention display, and the peep prevention film layer has a mesh structure; meshes of the mesh structure are arranged corresponding to sub-pixel units or pixel units of the display, and the peep prevention film layer comprises a P electrode lead layer, a P type semiconductor layer, an N type semiconductor layer and an N electrode lead layer. Since the peep prevention display has a small display angle of view, it can prevent peep by a person from side angle of view while providing image display for a user viewing from the front, so as to effectively protect personal privacy and business secret. In addition, the light blocked by a peep prevention film layer can be converted to electric energy, thus achieving an effect of self electricity generation.

Abstract: A pixel structure in an organic light emitting display panel includes a plurality of pixels. Each pixel includes a first sub-pixel, a second sub-pixel, and a third sub-pixel. Lengths of the first sub-pixel, the second sub-pixel, and the third sub-pixel are arranged along a first direction. Widths of the first sub-pixel, the second sub-pixel, and the third sub-pixel is arranged along a second direction. A length of the first sub-pixel is greater than a length of the second sub-pixel along the first direction and a length of the third sub-pixel along the first direction. The first sub-pixel, the second sub-pixel, and the third sub-pixel are orderly arranged along the second direction.

Abstract: A multi-tier memory device is formed over a substrate such that memory stack structures extend through an alternating stack of insulating layers and electrically conductive layers within each tier. Bit lines are formed between an underlying tier having drain regions over semiconductor channels and an overlying tier having drain regions under semiconductor channel, such that the bit lines are shared between the underlying tier and the overlying tier. Source lines can be formed over each tier in which source regions overlie semiconductor channels and drain regions. If another tier is present above the source lines, the source lines can be shared between two vertically neighboring tiers.

Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

Abstract: A driver integrated circuit chip includes a plurality of monitoring bumps, a plurality of output bumps, a plurality of first inner wires electrically connected to the output bumps, a plurality of second inner wires, and a plurality of switching circuits are electrically connected to the second inner wires. Each of the second inner wires is electrically connected between an adjacent pair of monitoring bumps. Each of the switching circuits controls a connection between adjacent monitoring bumps.

Abstract: The present invention provides a method for forming a semiconductor structure, comprising: firstly, a substrate is provided, next, a first dry etching process is performed, to form a recess in the substrate. Afterwards, an ion implantation process is performed to a bottom surface of the recess, a wet etching process is then performed, to etch partial sidewalls of the recess, so as to form at least two tips on two sides of the recess respectively, and a second dry etching process is performed, to etch partial bottom surface of the recess, wherein after the second dry etching process is performed, a lower portion of the recess has a U-shaped cross section profile.

Abstract: An imager is provided that includes an integrated circuit. The integrated circuit includes at least one metal layer, a signal line extending in a first direction, and a pixel cell. The pixel cell includes imaging pixels and a metal interconnect. The imaging pixels include first, second, third, and fourth imaging pixels, arranged in two rows and two columns, each imaging pixel having a metal-insulator-metal (MiM) capacitor disposed on the at least one metal layer, the first and second imaging pixels being traversed by the signal line to receive signals from the signal line. The metal interconnect extends in a second direction different than the first direction and is coupled to the signal line and the third imaging pixel to transmit the signals to the third imaging pixel. The third imaging pixel is adjacent to the first imaging pixel and is disposed in a different column or row than the second imaging pixel.