Abstract: A semiconductor device such as a FinFET includes a plurality of fins formed upon a substrate and a gate covering a portion of the fins. Diamond-shaped volumes are formed on the sidewalls of the fins by epitaxial growth which may be limited to avoid merging of the volumes or where the epitaxy volumes have merged. Because of the difficulties in managing merging of the diamond-shaped volumes, a controlled merger of the diamond-shaped volumes includes depositing an amorphous semiconductor material upon the diamond-shaped volumes and a crystallization process to crystallize the deposited semiconductor material on the diamond-shaped volumes to fabricate controllable and uniformly merged source drain.

Abstract: A semiconductor device includes a semiconductor chip, a wiring on the chip, an insulating film coating the wiring and having an opening partially exposing the wiring, a Ti/W film on a portion of the wiring facing the opening, a Cu layer on the Ti/W film and the wiring's exposed portion, and having a peripheral edge protruding away from the opening more than Ti/W film's peripheral edge in parallel to an insulating film surface, and a solder ball bonded to the Cu layer. The protrusion of the Cu layer's peripheral edge with respect to the Ti/W film's peripheral edge is greater than the Ti/W film's thickness. The Ti/W film's surface doesn't vertically surpass the Cu layer's upper surface in the opening's center. A Cu layer/solder ball interface is arc-shaped on both sides of the Cu layer's upper surface in a cross section taken perpendicularly to the Cu layer's upper surface.

Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks disposed side by side in a first direction, and a driver disposed on one end of the memory cell array in a second direction orthogonal to the first direction. A source diffusion layer, which is common to the first and second blocks, is disposed in a semiconductor substrate, and a contact plug, which has a lower end connected to the source diffusion layer and an upper end connected to a source line disposed above at least three conductive layers, is interposed between the first and second blocks.

Abstract: A method to form a strain-inducing semiconductor region is described. In one embodiment, formation of a strain-inducing semiconductor region laterally adjacent to a crystalline substrate results in a uniaxial strain imparted to the crystalline substrate, providing a strained crystalline substrate. In another embodiment, a semiconductor region with a crystalline lattice of one or more species of charge-neutral lattice-forming atoms imparts a strain to a crystalline substrate, wherein the lattice constant of the semiconductor region is different from that of the crystalline substrate, and wherein all species of charge-neutral lattice-forming atoms of the semiconductor region are contained in the crystalline substrate.

Abstract: The present invention provides a manufacture method of a TFT substrate, and the method comprises steps of: 1, deposing a first metal layer (2) on a substrate (1); 2, coating a first photoresistor layer (3) and implementing gray scal exposure; 3, removing a part of the first metal layer (2) to form a gate (21) and a source/a drain (23); 4, implementing ashing process to the first photoresistor layer (3); 5, deposing an isolation layer (4); 6, removing a part of the first photoresistor area (3) and a part of the isolation layer (4); 7, forming an oxide semiconductor layer (5); 8, deposing a protecting layer (6); 9, coating a second photoresistor layer (7) and implementing gray scal exposure; 10, removing a part of the protecting layer (6); 11, implementing ashing process to the second photoresistor layer (7); 12, deposing a transparent conducting thin film (8); 13, removing a part of second photoresistor layer (7) and a part of the transparent conducting thin film (8); 14, forming a pixel definition layer (9);

Abstract: The present invention is directed to a magnetic random access memory element that includes a multilayered seed structure formed by interleaving a first type sublayer and a second type sublayer to form one or more repeats of a unit bilayer structure and a first magnetic layer formed on top of the multilayered seed structure. The unit bilayer structure is made of the first and second type sublayers with at least one of the first and second type sublayers including therein one or more ferromagnetic elements. The multilayered seed structure may be amorphous or non-magnetic or both. The unit bilayer structure may be made of CoFeB and Ta sublayers.

Abstract: The present invention provides a semiconductor structure, which includes a substrate, at least two gate structures disposed on the substrate, a first recess, disposed in the substrate between two gate structures, the first recess having a U-shaped cross section profile, and a second recess, disposed on the first recess, the second recess having a polygonal shaped cross section profile, and has at least two tips on two sides of the second recess, the first recess and the second recess forming an epitaxial recess.

Abstract: A process of manufacturing an LED lamp strip includes the steps of forming a plurality of through holes on an adhesive tape, mounting the adhesive tape to a top side of a scrollable lead frame, bonding a plurality of LED chips to the top side of the scrollable lead frame according to the positions of the through holes, packaging the LED chips respectively, and finally cutting the scrollable lead frame. In light of this, the LED lamp strip can be produced under the circumstances of low production cost and less production time.

Abstract: A magnetic element and a magnetic memory utilizing the magnetic element are described. A contact is electrically coupled to the magnetic element. The magnetic element includes pinned, nonmagnetic spacer, and free layers and a perpendicular capping layer adjoining the free layer and the contact. The free layer has an out-of-plane demagnetization energy and a perpendicular magnetic anisotropy corresponding to a perpendicular anisotropy energy that is less than the out-of-plane demagnetization energy. The nonmagnetic spacer layer is between the pinned and free layers. The perpendicular capping layer induces at least part of the perpendicular magnetic anisotropy. The free layer is switchable between magnetic states when a write current is passed through the magnetic element. The free layer includes ferromagnetic layers interleaved with capping layer(s) such that a ferromagnetic layer resides at an edge of the free layer.

Abstract: A silicon carbide device includes an epitaxial silicon carbide layer including a first conductivity type and a buried lateral silicon carbide edge termination region located within the epitaxial silicon carbide layer including a second conductivity type. The buried lateral silicon carbide edge termination region is covered by a silicon carbide surface layer including the first conductivity type.

Abstract: A semiconductor package includes a wiring substrate including a plurality of solder pads; a chip including a plurality of chip pads connected to the solder pads through a plurality of solders; a sealing layer configured to seal the chip and the solders, at least one void being between the solders; and a solder extrusion prevention layer on one sidewall of the solder exposed by the at least one void.

Abstract: A pre-patterned substrate has a supporting material, a plurality of segments on the supporting material, a plurality of interdigitated line structures within each segment to allow formation of features, and an isolation region between the segments.

Abstract: Fluorine-induced formation of voids and electrical shorts can be avoided by forming fluorine-free metal lines. Specifically, control gate electrodes of a three-dimensional memory device can be formed employing fluorine-free deposition processes. Fluorine-free tungsten nitride can be deposited as a metallic barrier liner employing atomic layer deposition. Fluorine-free tungsten nucleation layer can be subsequently deposited. Fluorine-free tungsten fill process can be employed to form the control gate electrodes. The fluorine-free control gate electrodes do not include fluorine therein, and thus, circumvents yield and reliability issues associated with residual fluorine that are present in fluorine-containing metal lines.

Abstract: A device includes a first semiconductor layer, and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer and the second semiconductor layer comprise different materials. A semiconductor region is overlying and contacting the second semiconductor layer, wherein a bottom surface of the semiconductor region contacts a first top surface of the second semiconductor layer. The semiconductor region and the second semiconductor layer comprise different material. The bottom surface of the semiconductor region has a slanted portion contacting a (551) surface plane of the second semiconductor layer.

Abstract: A device includes a display panel configured to display one or more interfaces. The device includes one or more motion sensors. The device includes circuitry configured to determine, based on an input from the one or more motion sensors, a tilt angle of the device. The circuitry is configured to select, based on the determined tilt angle, an interface, of the one or more interfaces, and to control the display panel to display the selected interface.

Abstract: A method of forming an integrated circuit includes forming a gate electrode over a substrate, forming a recess in the substrate and adjacent to the gate electrode, forming a diffusion barrier structure in the recess, forming an N-type doped silicon-containing structure over the diffusion barrier structure and thermally annealing the N-type doped silicon-containing structure. The diffusion barrier structure includes a first portion and a second portion. The first portion is adjacent to the gate electrode and the second portion is distant from the gate electrode. The first portion of the diffusion barrier structure is configured to partially prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate and the second portion of the diffusion barrier structure is configured to substantially completely prevent N-type dopants of the N-type doped silicon-containing structure from diffusing into the substrate.

Abstract: A method of manufacturing a semiconductor device, includes providing a multi-chip interconnection substrate having an upper surface and a lower surface, providing a semiconductor chip having a main surface and a back surface, making the back surface of the semiconductor chip and the upper surface of the multi-chip interconnection substrate face each other and mounting the semiconductor chips in the chip mounting areas of the multi-chip interconnection substrate through a bonding adhesive, coupling the electrode pads formed on the main surface of each of the semiconductor chips with the bonding pads formed on the upper surface of the multi-chip interconnection substrate by the conductive wires respectively, forming a resin sealing body by resin-sealing the semiconductor chips, the conductive wires, and the upper surface of the multi-chip interconnection substrate, and forming a plurality of solder balls to be coupled to a plurality of bump lands formed on the lower surface of the multi-chip interconnection sub

Abstract: According to one embodiment, a semiconductor light emitting device includes a stacked structure body and an electrode. The stacked structure body has a first conductivity type first semiconductor layer including a nitride-based semiconductor, a second conductivity type second semiconductor layer including a nitride-based semiconductor, and a light emitting layer provided between the first and second semiconductor layers. The electrode has first, second and third metal layers. The first metal layer is provided on the second semiconductor layer and includes silver or silver alloy. The second metal layer is provided on the first metal layer and includes at least one element of platinum, palladium, rhodium, iridium, ruthenium, osmium. The third metal layer is provided on the second metal layer. A thickness of the third metal layer along a direction from the first toward the second semiconductor layer is equal to or greater than a thickness of the second metal layer.

Abstract: The present invention relates to an OLED device and a corresponding display apparatus, which includes a metal cathode; an organic emitter layer which is disposed on the metal cathode; a transparent cathode which is disposed on the organic emitter layer; and a reflective layer which is disposed between the metal cathode and the organic emitter layer. The reflective layer is an Ag—Mg—Cu alloy layer. The OLED device and the corresponding display apparatus of the present invention have low production cost and high light outputted efficiency.

Abstract: A semiconductor-storage-device manufacturing method of the present invention is a method for manufacturing a semiconductor storage device provided with a ferroelectric capacitor including a lower electrode, a ferroelectric film, and an upper electrode, and the method includes a step of embedding a first metal plug and a second metal plug in an insulating layer; a step of forming a covering layer that covers at least the second metal plug while securing a part that comes into electric contact with the first metal plug; a step of forming a deposit structure by sequentially depositing a material for the lower electrode, a material for the ferroelectric film, and a material for the upper electrode after forming the covering layer; and a step of forming the ferroelectric capacitor by etching and removing other parts except a part of the deposit structure such that the part of the deposit structure remains on the first metal plug.