Abstract: Structures including a tensile-stressed silicon arsenic layer, devices including the structures, and methods of forming the devices and structures are disclosed. Exemplary tensile-stressed silicon arsenic layer have an arsenic doping level of greater than 5 E+20 arsenic atoms per cubic centimeter. The structures can be used to form metal oxide semiconductor devices.

Abstract: A semiconductor device is manufactured by using an SOI substrate having an insulating layer on a substrate and a semiconductor layer on the insulating layer. The semiconductor device is provided with a gate electrode formed on the semiconductor layer via a gate insulating film, a sidewall spacer formed on a sidewall of the gate electrode, a semiconductor layer for source/drain that is epitaxially grown on the semiconductor layer, and a sidewall spacer formed on a sidewall of the semiconductor layer.

Abstract: A method and apparatus are provided for generating a personalized radio channel playlist by simultaneously buffering tracks from multiple received channels from one or more source streams and selectively playing back tracks from the buffered channels. Navigation tools permit users to skip buffered songs in their playlist (e.g., skip forward and backward). Users can specify favorite channels for building personal playlists, or multiple default playlist channels can be provided (e.g., by genre). Thumbs up/down buttons on the radio receiver permit entering a song or artist being played back into a favorites list that is used to search all channels for matches or a banned list used to block songs from future playlists. A matched channel carrying the favorite can be added to a playlist. Segments on the playlist can be played back in full or truncated to facilitate preview of playlist segments.

Abstract: The present disclosure relates to a split gate flash memory cell. In some embodiments, the split gate flash memory cell has a select gate separated from a semiconductor substrate by a gate dielectric layer. A control gate is arranged at one side of the select gate. A charge trapping layer has a vertical portion disposed between the select gate and the control gate, and a lateral portion extending under the control gate. A first control gate spacer is arranged on the lateral portion of the charge trapping layer and extends continuously along an outer sidewall of the control gate. A second control gate spacer is arranged on the lateral portion of the charge trapping layer and extends along an outer sidewall of the first control gate spacer. Bottom surfaces of the first and second control gate spacers are substantially co-planar with a bottom surface of the control gate.

Abstract: A phosphor-containing resin molded body and a wavelength conversion member, in each of which one or more kinds of spherical phosphors represented by (AxByCz)3C5O12 (wherein A represents one or more rare earth elements selected from among Y, Gd and Lu; B represents one or more rare earth elements selected from among Ce, Nd and Tb; C represents Al and/or Ga; and x, y and z respectively represent positive numbers satisfying 0.002?y?0.2, 0<z?2/3 and x+y+z=1) and having an average circularity of 0.3 or less are dispersed in an amount of 0.1-20% by mass; a light emitting device which is provided with the wavelength conversion member; and a resin pellet for phosphor-containing resin molded bodies.

Abstract: A circuit interconnecting substrate manufacturing method includes depositing a first layer of metallic powder on top of a carrier, and then forming a first layer of electrically conductive traces from the first layer of metallic powder. A second layer of metallic powder is then deposited onto at least one region of the first layer of electrically conductive traces. Then a second layer of electrically conductive traces is formed from the second layer of metallic powder and each trace of the second layer is electrically coupled to a trace of the first layer. An insulating material is deposited onto the carrier to provide an insulating substrate that supports the traces. The method does not require the use of any wet chemicals or chemical etching steps.

Abstract: An interconnect and a method of forming an interconnect for a semiconductor device is provided. The interconnect is formed by treating an upper surface of a dielectric layer to create a high density layer. The treatment may include, for example, creating a high density monolayer using hexamethyldisilazane (HMDS), trimethylsilydiethylamine (TMSDEA) or trimethylsilylacetate (OTMSA). After treating, the dielectric layer may be patterned to create openings, which are subsequently filled with a conductive material. Excess conductive material may be removed using, for example, a chemical mechanical polishing.

Abstract: A method of introducing N/P dopants in PMOS and NMOS fins at the SSRW layer without complicated processing and the resulting device are provided. Embodiments include forming a plurality of p-type and n-type fins on a substrate, the plurality of p-type and n-type fins formed with an ISSG or pad oxide layer; performing an n-well implant into the substrate through the ISSG or pad oxide layer; performing a first SRPD on the ISSG or pad oxide layer of the plurality of p-type fins; performing a p-well implant into the substrate through the ISSG or pad oxide layer; performing a second SRPD on the ISSG or pad oxide layer of the plurality of n-type fins; and driving the n-well and p-well implants and the SRPD dopants into a portion of the plurality of p-type and n-type fins.

Abstract: A semiconductor memory device according to an embodiment comprises: a memory cell array, the memory cell array including: a conductive layer, an inter-layer insulating layer, and a conductive line stacked on a semiconductor substrate in a stacking direction; first and second connecting lines that contact the semiconductor substrate and are electrically connected to the conductive line and that extend in the stacking direction; and a columnar body that penetrates the conductive layer and the inter-layer insulating layer in the stacking direction between the first and second connecting lines and that includes a first semiconductor layer, the semiconductor substrate having: a first impurity region to which a first impurity is added at a place of contact with the first connecting line; and a second impurity region to which a second impurity different from the first impurity is added at a place of contact with the second connecting line.

Abstract: An optical apparatus includes a substrate 1, a wiring pattern 8 formed on the substrate 1, a light-receiving element 3 and a light-emitting element 2 provided on the substrate 1 and spaced apart from each other in a direction x, a light-transmitting resin 4 covering the light-receiving element 3, a light-transmitting resin 5 covering the light-emitting element 2, and a light-shielding resin 6 covering the light-transmitting resin 4 and the light-transmitting resin 5. The wiring pattern 8 includes a first light-blocking portion 83 interposed between the light-shielding resin 6 and the substrate 1 and positioned between the light-receiving element 3 and the light-emitting element 2 as viewed in x-y plane. The first light-blocking portion 83 extends across the light-emitting element 2 as viewed in the direction x.

Abstract: An optical semiconductor device includes a metal lead frame including first and second plate portions, an optical semiconductor element mounted on the metal lead frame, and a reflector provided around the optical semiconductor element. A material for the reflector is an epoxy resin composition containing: (A) an epoxy resin; (B) a curing agent; (C) a white pigment; (D) an inorganic filler; and (E) at least one of a carboxylic acid and water. Components (C) and (D) are present in a total proportion of 69 to 94 wt % based on the amount of the overall epoxy resin composition, and the component (E) is present in a proportion of 4 to 23 mol % based on the total amount of the components (B) and (E). The resin composition has a higher glass transition temperature, and is excellent in moldability and blocking resistance and substantially free from warpage.

Abstract: A method of forming a semiconductor device that includes forming a high-k dielectric fin liner on the first plurality of fin structures in a first device region and a second plurality of fin structures in a second device region, and forming a gate structure including a low-k dielectric gate sidewall spacer on the channel region of the first and second plurality of fin structures. A first epitaxial semiconductor material on the first plurality of fin structures from which the high-k dielectric fin liner has been removed. The first epitaxial semiconductor material is then oxidized, and a remaining portion of the high-k dielectric fin liner is removed. A second epitaxial semiconductor material is formed on the second plurality of fin structures.

Abstract: An IC may include a substrate and a layer, and an array of GMAPDs in the layer. The layer may have trenches extending between adjacent GMAPDs. The IC may include an optically reflective material within the trenches. The optically reflective material may also be electrically conductive. For example, the optically reflective material may comprise a metal. Also, the trenches may be arranged in a honeycomb pattern.

Abstract: An SMD includes a substrate and one or more electrical contacts on a first surface of the substrate. Each one of the electrical contacts are configured to couple to a corresponding electrical contact located on a surface of a carrier, and are located within a concentric area of the first surface that is less than about 50% of a total area of the first surface. By providing the electrical contacts within the concentric area, the mechanical stress experienced by the electrical contacts can be significantly reduced when compared to conventional SMDs including electrical contacts on the outer edges thereof. Accordingly, the failure rate of the SMD due to separation of one or more of the electrical contacts from the carrier may be reduced.

Abstract: A multiple field plate transistor includes an active region, with a source, a drain, and a gate. A first spacer layer is over the active region between the source and the gate and a second spacer layer over the active region between the drain and the gate. A first field plate on the first spacer layer is connected to the gate. A second field plate on the second spacer layer is connected to the gate. A third spacer layer is on the first spacer layer, the second spacer layer, the first field plate, the gate, and the second field plate, with a third field plate on the third spacer layer and connected to the source. The transistor exhibits a blocking voltage of at least 600 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 5.0 m?-cm2, of at least 600 Volts while supporting a current of at least 3 Amps with an on resistance of no more than 5.3 m?-cm2, of at least 900 Volts while supporting a current of at least 2 Amps with an on resistance of no more than 6.

Abstract: An integrated circuit (IC) module for an IC card includes a plurality of IC card contacts in side-by-side relation. A dielectric support layer is above the contact layer and has a plurality of openings and a first coefficient of thermal expansion (CTE). An IC die is above the dielectric support layer and includes a plurality of bond pads. A bond wire extends from a respective bond pad to a corresponding contact through an adjacent opening in the dielectric support layer. A respective body of fill material is within each opening and has a second CTE. A mold compound body is above the dielectric support layer, the bodies of fill material, and surrounding the IC die. The mold compound body has a third CTE. The first CTE is closer to the second CTE than to the third CTE.

Abstract: The present invention is directed to a magnetic random access memory element that includes a multilayered seed structure formed by interleaving a first type sublayer and a second type sublayer to form one or more repeats of a unit bilayer structure and a first magnetic layer formed on top of the multilayered seed structure. The unit bilayer structure is made of the first and second type sublayers with at least one of the first and second type sublayers including therein one or more ferromagnetic elements. The multilayered seed structure may be amorphous or non-magnetic or both. The unit bilayer structure may be made of CoFeB and Ta sublayers.

Abstract: A semiconductor structure containing a vertical transistor having air gap spacers located above and below each functional gate structure is provided. Notably, a bottom air gap spacer is located between a bottommost surface of first and second functional gate structures and a topmost surface of a bottom source/drain region, and a top air gap spacer is located between a topmost surface of the first and second functional gate structures and a surface of the top source/drain region.

Abstract: In a transistor having a top-gate structure in which a gate electrode layer overlaps with an oxide semiconductor layer which faints a channel region with a gate insulating layer interposed therebetween, when a large amount of hydrogen is contained in the insulating layer, hydrogen is diffused into the oxide semiconductor layer because the insulating layer is in contact with the oxide semiconductor layer; thus, electric characteristics of the transistor are degraded. An object is to provide a semiconductor device having favorable electric characteristics. An insulating layer in which the concentration of hydrogen is less than 6×1020 atoms/cm3 is used for the insulating layer being in contact with oxide semiconductor layer which forms the channel region. Using the insulating layer, diffusion of hydrogen can be prevented and a semiconductor device having favorable electric characteristics can be provided.

Abstract: A wire of an embodiment includes: a substrate; a metal film provided on the substrate; a metal part provided on the metal film; and graphene wires formed on the metal part, wherein the graphene wire is electrically connected to the metal film, and the metal film and the metal part are formed using different metals or alloys from each other.