Abstract: Some embodiments of the present invention relate to a semiconductor device and a method of manufacturing a semiconductor device capable of preventing the deterioration of electrical characteristics. A p-type collector region is provided on a surface layer of a backside surface of an n-type drift region. A p+-type isolation layer for obtaining reverse blocking capability is provided at the end of an element. In addition, a concave portion is provided so as to extend from the backside surface of the n-type drift region to the p+-type isolation layer. A p-type region is provided and is electrically connected to the p+-type isolation layer. The p+-type isolation layer is provided so as to include a cleavage plane having the boundary between the bottom and the side wall of the concave portion as one side.

Abstract: Embodiments of the disclosure provide a mask, a mask group, a manufacturing method of pixels and a pixel structure. The mask includes a shielding region and an opening region which are alternately arranged. A width of the opening region is twice of a width of one sub pixel, and a width of the shielding region between two adjacent opening regions is four times of the width of one sub pixel.

Abstract: In various embodiments, a device is provided. The device includes a substrate having a first side and a second side opposite the first side. The substrate includes a plurality of driver circuits at the first side of the substrate. Each of the plurality of driver circuits is configured to drive a current from the first side of the substrate to the second side of the substrate. The device further includes at least one load interface at the second side of the substrate. The at least one load interface is configured to couple the current from the plurality of the driver circuits to a plurality of loads at the second side of the substrate.

Abstract: It is an object to provide a wireless chip which can increase a mechanical strength, and a wireless chip with a high durability. A wireless chip includes a transistor including a field-effect transistor, an antenna including a dielectric layer sandwiched between conductive layers, and a conductive layer connecting the chip and the antenna. Further, a wireless chip includes a transistor including a field-effect transistor, an antenna including a dielectric layer sandwiched between conductive layers, a sensor device, a conductive layer connecting the chip and the antenna, and a conductive layer connecting the chip and the sensor device. Moreover, a wireless chip includes a transistor including a field-effect transistor, an antenna including a dielectric layer sandwiched between conductive layers, a battery, a conductive layer connecting the chip and the antenna, and a conductive layer connecting the chip and the battery.

Abstract: Described herein is device configured to be a solar-blind UV detector comprising a substrate; a plurality of pixels; a plurality of nanowires in each of the plurality of pixel, wherein the plurality of nanowires extend essentially perpendicularly from the substrate.

Abstract: A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased.

Abstract: An organic light emitting display includes an array substrate, a plurality of light emitting devices disposed over the array substrate, and a plurality of color filters having different colors. The plurality of light emitting devices include a first light emitting device configured to emit light having a first color and a second light emitting device configured to emit light having a second color different from the first color, and the plurality of color filters include first and second color filters disposed over the first light emitting device and the second light emitting device, respectively.

Abstract: The invention discloses a treatment process for a semiconductor, comprising providing a substrate; defining a trench opening region of the substrate; performing plasma etching to form a trench region at the trench opening region; subjecting the substrate to a first epitaxial process with a first plurality of gaseous species to form a protective layer overlaying at least the first sidewall and the bottom of the trench region; and subjecting the substrate and the protective layer to a second epitaxial process with a second plurality of gaseous species to form a filling material overlaying the protective layer and being positioned at least partially within the trench region. The invention further provides a semiconductor processing technique used to eliminate or reduce dislocation defect on the semiconductor device and improve device performance.

Abstract: A semiconductor device may include a first subassembly and a second subassembly. The first subassembly may include a first bonding layer. The second subassembly may include a second substrate and a second bonding layer directly bonded to the first bonding layer. The first bonding layer and the second bonding layer may be lattice-mismatched to one another. At least one of the following may be selected: the first bonding layer is lattice-mismatched to the first substrate, and the second bonding layer is lattice-mismatched to the second substrate.

Abstract: Structures including a tensile-stressed silicon arsenic layer, devices including the structures, and methods of forming the devices and structures are disclosed. Exemplary tensile-stressed silicon arsenic layer have an arsenic doping level of greater than 5 E+20 arsenic atoms per cubic centimeter. The structures can be used to form metal oxide semiconductor devices.

Abstract: Provided are superconducting tunnel junctions, such as Josephson tunnel junctions, and a method of fabricating thereof. A junction includes an insulator disposed between two superconductors. The junction may also include one or two interface layers, with each interface layer disposed between the insulator and one of the superconductors. The interface layer is configured to prevent oxygen from entering the adjacent superconductor during fabrication and operation of the junction. Furthermore, the interface layer may protect the insulator from the environment during handling and processing of the junction, thereby allowing vacuum breaks after the interface layer is formed as well as new integration schemes, such as depositing a dielectric layer and forming a trench in the dielectric layer for the second superconductor. In some embodiments, the junction may be annealed during its fabrication to move oxygen from the superconductors and/or from the insulator into the one or two interface layers.

Abstract: A display device is provided that comprises a pattern positioned on a substrate, the pattern comprising a multi-layered structure comprising a conductive layer and at least one light-blocking layer in whole or in part; and a bank positioned on the pattern, the bank comprising a light-absorbent material.

Abstract: A semiconductor device and method of making a semiconductor device are disclosed. A semiconductor body, a floating gate poly and a source/drain region are provided. A metal interconnect region with a control gate node is provided that capacitively couples to the floating gate poly.

Abstract: A embodiment package includes a three dimensional integrated circuit (3D IC) with first input/output pads on a first side and second input/output pads on a second side, a first fan out structure electrically coupled to the first input/output pads on the first side of the three dimensional integrated circuit, and a second fan out structure electrically coupled to the second input/output pads on the second side of the three dimensional integrated circuit.

Abstract: A source and drain electrode layer (3s/3d) of an oxide TFT element (3) is formed by a first conductive layer. A gate electrode (3g) of the oxide TFT element (3) and a gate electrode (5g) of an a-Si TFT element (5) are formed by a single conductive layer, that is, a second conductive layer. A source and drain electrode layer (5s/5d) of the a-Si TFT element (5) is formed by a third conductive layer. The third conductive layer is formed above the second conductive layer in a thickness direction in which each conductive layer is stacked on an insulating substrate (2). Further, the first conductive layer is formed below the second conductive layer in the thickness direction. Therefore, it is possible to provide a circuit board that can have an improved degree of integration of transistor elements formed on the insulating substrate.

Abstract: A method for fabricating an EDLC includes (a) coating a porous activated carbon material onto current collector sheets to form carbon-based electrodes, (b) drying the carbon-based electrodes, (c) winding or stacking carbon-based electrodes interleaved with separator sheets to fabricate a jelly roll or prismatic electrode assembly, (d) inserting the electrode assembly into a package and forming electrical connections between the electrode assembly and package terminals, (e) filling the package with a liquid electrolyte, and (f) sealing the package. Steps (a)-(f) are performed in an atmosphere having a low moisture content. The atmosphere may be vacuum or purged with dry gas.

Abstract: A light-emitting device, comprising: a substrate; a semiconductor stacking layer comprising a first type semiconductor layer on the substrate, an active layer on the first semiconductor layer, and a second semiconductor layer on the active layer; and an electrode structure on the second semiconductor layer, wherein the electrode structure comprises a bonding layer, a conductive layer, and a first barrier layer between the bonding layer and the conductive layer; wherein the conductive layer has higher standard oxidation potential than that of the bonding layer.

Abstract: In accordance with some embodiments, systems and methods for processing a semiconductor substrate are provided. The method includes loading a semiconductor substrate from a chamber to a transfer module, detecting a center and a notch of the semiconductor substrate by the transfer module, and transferring the semiconductor substrate from the transfer module to a process chamber.

Abstract: A device includes a crystalline material within an area confined by an insulator. A surface of the crystalline material has a reduced roughness. One example includes obtaining a surface with reduced roughness by using a planarization process configured with a selectivity of the crystalline material to the insulator greater than one. In a preferred embodiment, the planarization process uses a composition including abrasive spherical silica, H2O2 and water. In a preferred embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique.

Abstract: A magnetic sensor includes a plurality of groups, each group comprising a plurality of magnetic tunnel junction (MTJ) devices having a plurality of conductors configured to couple the MTJ devices within one group in parallel and the groups in series enabling independent optimization of the material resistance area (RA) of the MTJ and setting total device resistance so that the total bridge resistance is not so high that Johnson noise becomes a signal limiting concern, and yet not so low that CMOS elements may diminish the read signal. Alternatively, the magnetic tunnel junction devices within each of at least two groups in series and the at least two groups in parallel resulting in the individual configuration of the electrical connection path and the magnetic reference direction of the reference layer, leading to independent optimization of both functions, and more freedom in device design and layout.