Abstract: A device includes, a reconfigurable baseband filter configured to receive a communication signal having a first carrier and a second carrier, the first carrier and the second carrier having non-contiguous respective frequencies, the reconfigurable baseband filter having a first filter portion and a second filter portion, the first filter portion and the second filter portion each comprising respective first and second amplification stages, and a plurality of switches associated with the first filter portion and the second filter portion, the plurality of switches for configuring the reconfigurable baseband filter into a plurality of sub-filters, each configured to generate at least one of a low pass filter output and a bandpass filter output.

Abstract: Speech signals coded according to the principle of high-resolution long-term prediction (HLTP) have a high accuracy due to the high-resolution which causes a high complexity. The ordinary LTP method is improved by use of oversampling and determining subsegments Cd lying in a preceding segment which precedes a subsegment to be coded, for which it is the case that the number of samples Dd, expressed in the numbers of samples after oversampling, between the initial time instant of the subsegment to be coded and the initial time instant of a subsegment Cd, fulfills the relation Dd=(D*Ob)/d, in which d=2,3,4 . . . n, where n is a positive integer and where Ob and n are chosen in a manner such that Dd is always an integer. Null sample values produced initially for oversampling are given significance by means of an interpolation technique, at predetermined positions which are situated at a spacing Dd from the original samples in the subsegment to be coded.

Abstract: An FIR digital filter of which impulse response S(t) meets an equation, S(t)=H(t)exp(j.omega.t), where H(t) represents roll off characteristics and .omega. is an arbitrary frequency. The filter includes a data storing device for delay storing real and imaginary number data of a plurality of binary complex input data, a coefficient storing device for storing real and imaginary number coefficients corresponding to s(0), s(1), . . . , s((N-1)/2) when N is an odd number, or s(0), s(1), . . . , s(N/2-1) when N is an even number. Where s(0) to s(n-1) represent an impulse response string. The filter also includes a reversible counting and reading out device for reading the real and imaginary number coefficients stored in the coefficient storing device in order of s(0), s(1), . . . , s((N-1)/2) ) at a first order and s((N-3)/2) ) , . . . , s(1), s(0) next at a second order when N is an odd number, or in order of s(0), s (1), . . . , s(N/2-1) ) at a first order and s(N/2-1) ) , . . .

Abstract: The spectral encoding-decoding system and method are for encoding a sequence of N data bits where N is a predetermined integer, into an information signal to be transmitted on a communication medium, and for decoding the information signal transmitted on the communication signal into an estimated sequence of N data bits. The system comprises an encoder and a decoder. The encoder receives the sequence of N data bits, encodes the sequence into the information signal, and emits the information on the communication medium. The decoder receives the information signal transmitted on the communication medium, decodes the information signal and transmits the estimated sequence of N data bits. The method corresponds to the operations performed by the system.

Abstract: A single-port network node transceiver that does not draw any substantial current from the network when it is powered-down, enabling it to meet the ISDN powered-down loading specification when built on a CMOS integrated circuit chip. The pull-up transistors of the transmitter output circuit each have means for shorting the well terminal to source terminal connection when the circuit is operating and opening the connection when the power to the transceiver is shut down. The opening of this connection prevents the well-substrate junction of the pull-up transistors from becoming forward biased and drawing current from the network when the power to the transceiver is off and there is voltage present on the network. The transceiver also includes a plurality of ESD overvoltage protection diodes in series between the power supply rail and each input/output terminal.

Abstract: A digital communication system including a Viterbi decoder for tracing a path through a trellis of individual state information and method of operation are disclosed. The traceback determines a decoded symbol. A trellis of branch origin data is stored in an array of registers. The branch origin data associated with a symbol instant is a cell. Each cell of data is generated by execution of an update instruction form a digital signal process (DSP) to the coprocessor. A first predetermined traceback length is written to a traceback length register. The first predetermined traceback length is small to minimize tracebacks cycling into branch origin data from a previous transmission burst. A traceback is initiated by the DSP providing the coprocessor a single traceback instruction. The Viterbi decoder alternates between update and traceback instructions. At a predetermined symbol instant, the traceback length is increased to a second predetermined length by over-writing the traceback length register.

Abstract: An apparatus for performing digital signal frequency translation in a digital receiver is disclosed. The apparatus uses a plurality of mixer-filter-decimator stages for performing the digital signal frequency translation. The translation function converts the digital signal to an intermediate frequency (IF), where such translation is distributed among the plurality of mixer-filter-decimator stages to thereby simplify the mixing requirements.

Abstract: A decoding method and apparatus having an optimum decoding path includes a Viterbi decoder having an overlapping function in which the input signal is moved in units of the window movement distance of at least one symbol and the code sequence is decoded in units representing a decoding depth, so that overlap in the decoded data occurs. Then, the output of the Viterbi decoder with the overlap function is stored in a memory. A control signal generator controls the positions of the data to be output from the memory according to the output of a counter receiving the decoded data. The most frequent data out of all data supplied to a comparator is selected as an optimum decoding path. Thus, the error associated with wrong path selection, e.g., when the data is wrongly decoded due to the error generated by the noise added during transmission, can be reduced.

Abstract: In a selectively called radio receiver in which a demodulated signal of a specific bit rate is produced with battery saving kept in synchronism with the demodulated signal, a bit rate detecting unit detects the bit rate with a controllable sensitivity while the synchronism is lost. A bit rate detecting control arrangement controls the sensitivity within a predetermined sensitivity range. The bit rate detecting unit may misdetect the bit rate with a variable misdetection rate which is accumulated to an incremented amount from an initial amount representative of no misdetection while the synchronism is lost. The bit rate detection control arrangement may decrement the misdetection rate to the initial amount when the incremented amount reaches a predetermined amount. Alternatively, the bit rate detection control arrangement may control the misdetection rate between a greater and a smaller amount and then cause the misdetection rate to return to the initial amount.

Abstract: A phase adjusting circuit for a demodulator is provided. The circuit comprises an A/D converter for sampling an input analog signal at an interval shorter than the Nyquist interval and converting the sampled analog signal to a digital signal, a digital filter for narrowing the frequency band of the digital signal to output a filtered digital signal, a digital sampling/holding circuit for decimating sampling components of the filtered digital signal to output a decimated digital signal, and a phase locked loop circuit for detecting a phase error of the decimated digital signal and controlling the number of sampling intervals to be skipped by the digital sampling/holding circuit.

Abstract: Signals in synchronizing sequences and data sequences are transmitted over a fading channel to a sequence estimation receiver. The signals are received by a plurality of mutually separated antennas and sampled to produce received antenna signals (S.sub.in,r (k)). Using the received antenna signals, part transmission channel estimates (h.sub.est,r) are formed for each antenna. These part channel estimates are used to form precomputed metric values (f.sub.a,r ((.DELTA.T.sub.ij),g.sub.a (.DELTA.T.sub.ij)). For the sequence estimation algorithm, branch metric values (m(.DELTA.T.sub.ij,k)) are formed by combining the precomputed metric values with the received antenna signals for state transitions (.DELTA.T.sub.ij). For one state transition there is formed a metric value such as the sum of a metric value (M(T.sub.j,k-1)) for an old state (T.sub.j) at a preceeding sampling time point (k-1) with a branch metric value (m(.DELTA.T.sub.ij,k)).

Abstract: A radio system having a master station including a wideband receiver, an A/D converter and a digital signal processing module for each of a plurality of space diversity antennas, the digital signal processing module converting the digitized samples into the frequency domain, weighting and combining the frequency domain signals from each of the antennas and separating the signals into signals corresponding to those transmitted from the remote stations.

Abstract: The present invention comprises an apparatus and method for substantially canceling impulsive noise from data. Such substantial cancellation is achieved by converting the time-domain data into its corresponding frequency spectrum, such that the impulsive noise threshold can be determined. Once such threshold is determined, all frequency components less than this threshold are canceled with the resulting spectrum being converted back to the time-domain. This substantially impulse free signal can then be substituted into the original signal where the impulsive noise occurs, thus, resulting in a signal having minimally distorted data that is substantially devoid of any impulsive noise. This signal may be further processed by an adaptive filter stage to substantially remove any remaining noise from the signal.

Abstract: A transmitting/receiving station having a section comprising a cellulating buffer for dividing input data into cell data of a plurality of channels on the basis of a cell having a predetermined bit length. Before the transmission of the cell data, a signal outputting section sends a synchronizing signal including particular channel identification data to each of the channels. As a receiving section of a receiving station receives the synchronizing signals, a signal detector distinguishes the channels while detecting the times when the channels were received. Then, the receiving section is initialized such that a replacing section transfers cell data other than those of a channel arrived last to a time gap buffer, and the time gap buffer corrects a difference between the reception timings of cell data.

Abstract: In a data communication system having a sending station and multiple receiving stations interconnected by a satellite or a local area network, the sending station transmits a request signal containing an assigned logical link number to the receiving stations. If the assigned logical link is available to each of the receiving stations, each receiving station establishes a logical link to the sending station and transmits an acknowledgement signal to the sending station. During a predetermined period following the transmission of the request signal, the sending station increments a count value in response to receipt of each acknowledgement signal. When the count value exceeds a threshold value, the sending station transmits a broadcast message over the established logical link to the receiving stations.

Abstract: A data communication circuit comprising a slave device (3), a master device (2) and a two-wire bus (6) wherein the master device (2) creates a potential difference (V(t)) between the two wires so as to provide power to the slave device (3). The slave device (3) comprises a pulse decoder (20) for detecting the pulses and producing a synchronisation signal (Clk) upon the detection of each pulse. The master device (2) also comprises a pulse control circuit (40) for causing the pulse creating circuit to create a series of data pulses having the same state when the digital information is read from the slave device (3). In addition, the slave device (3) further comprises a circuit (43,58) for changing the state of selected ones of the data pulses in the series in response to the digital information to be read.

Abstract: A phase-locked loop configuration includes a controllable delay device having a signal path with at least one inverter having supply lines, at least one field effect transistor having a load path, and at least one capacitor connecting the load path transversely to the signal path. A phase detector receives a reference signal and receives an input signal through the delay device. A first controller is connected downstream of the phase detector for controlling the load path of the at least one field effect transistor in the delay device. At least one pair of further field-effect transistors has load paths connected into the supply lines of the at least one inverter. A second controller is connected downstream of the phase detector for controlling the load paths of the further field effect transistors.

Abstract: A monolithic digital chirp synthesizer (DCS) chip using GaAs/AlGaAs HI.sup.2 L technology. The 6500 HBT gate DCS chip is capable of producing linear frequency modulated (chirp) waveforms or single frequency waveforms. The major components of the DCS are two pipelined accumulators, a sine ROM, a cosine ROM and two digital to analog converters.

Abstract: The present invention involves a device for synchronizing the broadcast frequency of a base station and a microcell linked together by a metallic medium as well as a method for using the device to synchronize the base oscillator and the microcell oscillator. The device comprises a base transmitter which transmits a base time-of-day signal to a microcell comparer, and a microcell clock which sends a microcell time-of-day signal to the microcell comparer. A microcell oscillator provides the microcell clock with a reference frequency. The microcell comparer calculates a time difference which represents a time difference between the base time-of-day signal and the microcell time-of-day signal. The microcell comparer then outputs a correction signal to a digital controller. The digital controller adjusts a microcell oscillator according to the correction signal.

Abstract: In a digital communication system (100), a second message (309) may be substituted for a first message (301) by detecting a suitable transition point and beginning transmission of the second message at this transition point. In a frame-synchronous digital communication system, this transition point is a frame boundary within the first message.