Abstract: A device (500) and method (400) for zero-padding constellation switching with frame mapping provides reduced complexity for mapping frames having possibly a fractional number of bits and a predetermined number of symbols while eliminating the usual disadvantages of constellation switching.

Abstract: A wireline bridge tap device and an associated signal processing mechanism are capable of successfully extracting and recovering the respective signalling components of a full-duplex wireline digital data link without having to disturb the link during its use (e.g. as by interrupting service to sever the link in order to install a line coupling device, such as a modem or attenuator pad to signal monitoring equipment). The full-duplex wireline bridge device comprises a signal characteristic monitoring device that is capable of monitoring the link and providing respective output signals representative of the respective unidirectional signal components being transmitted simultaneously in opposite directions along the link. A directional signal separator, comprised of a voltage probe and a current probe, each of which can be coupled to the link without severing the link or otherwise disrupting ongoing communications, couples the signal characteristic monitoring device to the link.

Abstract: In a radio communication apparatus comprising a demodulator (12) for demodulating a multilevel modulated signal (10) into a time sequence of multilevel symbols which have symbol levels to define a variable pattern by a level difference between the symbol levels of at least two successive adjacent ones of the multilevel symbols, a coincidence detecting section (16) detects coincidence between the variable pattern and a predetermined pattern and calculates judgement levels when the variable pattern coincides with the predetermined pattern with a tolerance. A multilevel-to-binary converter (14) converts the time sequence of multilevel symbols into a binary signal of binary values by judging the symbol levels on the basis of the judgement levels. Preferably, a variation following level calculating section (30) calculates variation following levels for use as the judgement levels by using the symbol levels, the binary values, and the judgement levels.

Abstract: A phase compensating circuit in a video signal processing system utilizing a frequency folding technique which requires the recovery of an exact sampling phase is disclosed. A predetermined pattern is inserted during an encoding operation, and the frequency of the inserted pattern is discriminated during a decoding. During this process, when a comparison is made as to whether the original phase lies at the front or at the rear of the received phase, the comparison is not made with an exact value, but with a predetermined range of values by taking into account the inherent variability in delay values, for example, due to temperature variations, of delaying devices of a clock adjusting part. In this regard, the sum total of the delays of the delaying devices is made to include one clock period by taking into account the temperature characteristics of the delaying devices, with the result that clocks having a relatively exact phase can be generated based on the pattern inserted during an encoding.

Abstract: A configuration generates a clock signal from a digital signal by evaluating signal edges of the digital signal. A first device generates a pulse at a signal edge oriented in a first direction, and a second device generates a pulse at a signal edge oriented in a second direction being opposite the first direction. Each of the devices has one terminal for receiving a digital signal and one output. A voltage-controlled, triggerable oscillator device has at least two trigger inputs, one control input and one output. Each of the trigger inputs is connected to the output of a respective one of the first and second devices, and the output of the oscillator device is an output for the clock signal. An integration device has an input connected to the output of the oscillator device and has an output connected to the control input of the oscillator device.

Abstract: An automatic equalizer is used in a radio transmission path for improving convergent characteristics of a control loop in an automatic equalizing mode when the amplitude ratio of reflected and direct waves is greater than 1. The automatic equalizer has an adaptive matched filter, a decision feedback equalizer, and a reset control circuit for outputting first and second reset signals, respectively, to the adaptive matched filter and the decision feedback equalizer when an asynchronous condition is detected. After the first and second reset signals are generated, thereby resetting the adaptive matched filter and the decision feedback equalizer simultaneously, the first reset signal is eliminated before the second reset signal is eliminated. The decision feedback equalizer is thus brought into the automatic equalizing mode after the adaptive matched filter has entered the automatic equalizing mode and symmetrized impulse responses.

Abstract: Timing loop apparatus and method are provided for data detection in a partial-response maximum-likelihood (PRML) data channel. The PRML data channel includes an analog to digital converter (ADC) providing samples to a digital filter during a tracking mode and to a gain and timing control during an acquisition mode. Sample values from the ADC are received at peaks and zeros on sync field pattern. An error absolute value is calculated from the received ADC sample values and an error sign of the calculated error absolute valve calculated using a most significant bit of the current and a previous sample. Timing correction values are calculated responsive to the calculated error absolute value and applied to a clock gated register that latches and holds the generated timing correction values for a predefined number of clock cycles.

Abstract: The feedforward filter section of a decision feedback equalizer is modified to include one or more postcursor taps, that are sequentially weighted at decreasing binary fractions of the cursor tap. Such a modified feedforward filter section, combined with the placement of a simple anti-aliasing filter upstream of the sampling point, results in an optimum feedforward filter configuration that is not anticausal, and offers a substantially improved performance over conventional DFB equalizer structures. Optimum performance is achieved when such a postcursor filter structure is augmented with an adaptive noise canceler coupled in the DFB path.

Abstract: An adaptive data separator for detecting systematic differences between the arrivals of the rising and falling edges of a digital signal and for compensating for the difference. Data packets from a transmission source are prefixed with two data bits of known values. The data separator is also supplied with four clock signals per bit, one corresponding to an ideal rising edge and three following every 5 nanoseconds. The two prefix bits preceding a data packet are then sampled at each of the clock signals. Since all information in a given data packet undergoes the same systematic distortion, the logic of the adaptive data separator can determine the optimum clock signal to use in sampling each bit of data for the packet. Through several multiplexers the incoming data is then clocked to the optimal clock signal for sampling.

Abstract: In a disclosed PLL circuit, a constant voltage output by a constant voltage power supply 6 for obtaining a signal with a frequency equivalent to that obtained in a synchronized state is added to a signal output by a filter 3 by means of an adder 7. A signal output by the adder 7 representing the sum of the voltage output by the constant-voltage power supply and the signal output by the filter is supplied to a voltage-controlled oscillator 4. With a reference signal Pi supplied, the PLL circuit functions like an ordinary PLL circuit. When the signal Pi becomes unavailable, however, a signal output by a reference-signal-input detecting circuit 5 for monitoring the reference signal Pi puts integrating components employed by the filter 3 in a short-circuit state, initializing information accumulated in the integrating components. In addition, the output of the filter is set to zero.

Abstract: Multilevel coded modulation equipment includes a transmission unit and a reception unit. The transmission unit includes a first converting unit, a first encoding unit, a first differential encoding unit, a second encoding unit, a mapping unit, and a modulating unit. The reception unit includes a demodulating unit, a first decoding unit, an inverting unit, a phase shifting unit, a second decoding unit, a differential decoding unit, a decision unit, and a second converting unit. The first converting unit distributes an input serial digital signal to a plurality of levels containing a level 1 indicating a level which is transparent to a 90.degree. phase ambiguity, and a level 2 indicating a level which is transparent to a 180.degree. phase rotation. The second converting unit receives outputs from the inverting unit, the differential decoding unit, and the decision unit, multiplexes the received signals into a serial digital signal, and outputs the serial digital signal.

Abstract: A transceiver for transmitting and receiving digital data represented as stair-stepped sinusoidal waveforms over twisted pair lines interconnecting nodes of a network. The transmitter of the transceiver converts square waves into the stair stepped sinusoidal waveforms by utilizing a number of current sources for supplying differing amounts of current to a resistor coupled across the twisted pair lines. Shift registers control a set of switches which control the direction and the amount of current flowing through the resistor. Thereby, the output voltage across the resistor can be controlled to produce the stair-stepped sinusoidal waveform by clocking the digital signal to the shift registers. The receiver of the transceiver re-converts received stair-stepped sinusoidal waveforms back to their respective digital signals.

Abstract: A digital radio communication system includes a receiver for receiving a signal stream that includes data frames, each frame including a data signal sequence and a synchronizing sequence. The communication system synchronizes the receiver by employing the signal stream and comprises: a sampling circuit for sampling symbol levels in the synchronizing signal sequence; cross correlation circuitry for comparing values derived from the sampled symbol levels with an expected set of values and producing an error value output; and correction circuitry that is responsive to the error output and produces a sample control output to the sample circuitry to alter the times of sampling of the symbol levels so as to reduce the error output and achieve time synchronization with the received synchronizing signal sequence.

Abstract: Viterbi detector for a channel having a memory length 1, where no more than two survivors with an associated difference metric are updated. In the prior-art Viterbi detector of this type the new difference metric is derived using a saturation function from the previous difference metric. If the amplitude of the received signal differs from the values assumed for the calculation of the difference metric, the performance of the prior-art detector will rapidly degrade. In the detector according to the invention the new difference metric is derived from a saturation function of the previous difference metric, with the size of the linear region being dependent on the magnitude of the amplitude of the received signal.

Abstract: In a receiver for use in demodulating a modulated wave modulated by a digital data signal arranged within a preselected channel to produce a reproduced data signal by the use of a local frequency signal of a local frequency, a VCO and a PLL circuit are intermittently put into active states with reference to an offset frequency between a channel frequency and the local frequency. The PLL circuit is put into the active state for a time interval determined by the offset frequency before reception of the preselected channel while the VCO is put into the active state during the active state of the PLL circuit and during reception of the preselected channel. A duration of the active state in the PLL circuit becomes long when the offset frequency does not fall within a predetermined range determined by predetermined offset frequencies and, otherwise, the duration of the active state in the PLL circuit becomes short.

Abstract: Punctured binary convolutional codes are used in a trellis coded modulation scheme to achieve spectral efficiencies as high as those of multi-dimensional codes, using simple hardware. A base rate 1/2 binary convolutional code is punctured to rate n/k. The output of the punctured encoder is mapped to a four-way partition of a 2.sup.N point two-dimensional QAM constellation. The four-way partition consists of a two-way partition in both the I and Q dimensions. The two-way partitions of each dimension are used to transmit the two level output of the rate n/k binary convolutional coder. (N-2) "uncoded" bits are transmitted by selecting the unique constellation point in a partition group. The code has an average throughput of (N-2)+2n/k bits per symbol. The invention is also applicable to trellis coded amplitude modulation schemes based on 2.sup.N possible amplitude levels provided along a one-dimensional constellation.

Abstract: In a communication system in which direct sequence spread spectrum modulation techniques are used interference is generated in communications by remote stations since the communications share the same frequency spectrum. In order to increase system capacity the power level of the remote station transmitters are controlled by the local station. A setpoint is generated by the local station and compared with the remote station signal strength measured at the local station. The result of this comparison is used to generate power level adjustment commands which are sent to the remote station. The remote station is responsive to the power level adjustment commands for increasing or decreasing remote station transmitter power. In a spread spectrum communication system in which data is encoded at variable data rates, the local station determines the rate at which received data was encoded by the transmitting remote station.

Abstract: A modem/codec is designed for a digital signal transmission system using a single satellite transponder. The system is capable of transmitting data of a rate of 155.52 Mbps, and is thus compatible with the BISDN rate. A codec of rate 13/15 is used, and an octal phase shift keying modem is also used. In this way, the digital signal transmission system is capable of receiving data at a rate of 155.52 Mbps over a single INTELSAT V/VA transponder with a usable bandwidth of 72 MHz.

Abstract: A multiple phase clock distribution system for allowing a circuit load to be clocked on predetermined phases of a single clock signal is provided. A single phase clock is the triggering signal for each circuit load in the system, and enable signals are provided to each circuit load to allow the single phase clock to be recognized at only upon an active logic level of the chosen enable signal at a particular circuit load. The enable signals are of duration equal to one period of the single phase clock, and are activated nearly one period of the single phase clock before the triggering edge of the clock to provide as long of an enable signal stabilization period as possible before the single phase clock transitions to its active logic level. Enable signal combination circuitry exists to combine individual enable signals so that varying-frequency enable signals can be produced, and can therefore emulate a multiple phase clock regardless of the number of phases desired.

Abstract: A magnetic recording apparatus includes a magnetic recording medium for recording a binary signal; a magnetic head for detecting the binary signal; an amplifier for amplifying the binary signal detected by the magnetic head; a channel for outputting the amplified binary signal in the form of a timing value sequence, the timing value sequence alternatively providing positive and negative peak values following the rule of the binary signal that recorded in the recording medium; a temporary judging unit for judging a presently input timing value of the timing value sequence supplied from the channel as one of the positive peak value, in accordance with the relationship with a preceding timing value temporarily judged as one of the positive and negative peak values; a final judging unit for finally setting the preceding timing value as one of the positive and negative peak values and the intermediate value, in accordance with the relationship with the presently input and temporarily judged timing value; a counter