Abstract: Supplied with an input signal into which a carrier signal is modulated at a frame period by a data signal and unique words periodically interspersed throughout the data signal, a demodulating circuit (14) demodulates the input signal into a demodulated signal. A frame synchronizing circuit (23) produces an aperture signal which defines an aperture interval determined by the frame period when the demodulated signal has a level which is lower than a predetermined threshold level. Responsive to the aperture signal, a cross-correlating circuit (24) calculates a cross-correlation coefficient between the demodulated signal and a locally known unique word. By the use of the cross-correlation coefficient, a phase error calculating circuit (25) calculates a phase error between a reproduced carrier signal reproduced from the demodulated signal and a regenerated carrier signal which is a correct regeneration of the carrier signal.

Abstract: A modulation circuit includes a mapping position detector as well as a circuit for differentially phase coding a plurality of separated data streams. The differentially phase coding circuit is adapted to differentially phase code the plurality of data streams for each pulse time and generate a coded signal containing amplitude information. The mapping position detector detects the phase mapping position of the coded signal based on the amplitude information in the coded signal which is output from the differentially phase coding circuit. Information representing the detected phase mapping position is supplied to the differentially phase coding circuit so as to achieve a differential phase coding at a pulse time following one pulse time.

Abstract: A timing circuit having an analog to digital converter to sample an analog signal, a controlled oscillator for controlling sample times of the analog to digital converter, a circuit to detect pulses in the analog signal, a phase error circuit to subtract one of two samples from the other to create a phase error measurement and a frequency error circuit to add two samples together to create a frequency error measurement. The two samples are taken from either side of a pulse. The phase error measurement is used by the controlled oscillator to adjust the sample timing to take samples at desired locations on the pulse. The circuit also contains constant values used to compensate for the pulse being asymmetrical and to compensate for other pulses that occur close to the detected pulse. The circuit also inserts a known frequency in place of the analog signal to establish a frequency of the controlled oscillator.

Abstract: In an adaptive matched filter with a decision feedback equalizer (DFE), a tap-weight controller of the matched filter includes a tapped delay line having a series of delay elements for receiving an incoming digital signal to produce successively delayed signals at successive taps of the delay line so that the signal at the center tap coincides with an output of the DFE. Cross-correlators are associated respectively with tap-weight multipliers of the matched filter. In each cross-correlator, cross-correlation is detected between a digital sample from the DFE and a delayed version of the corresponding digital sample. An average value is taken of the cross-correlation to produce higher significant bits of a tap-weight coefficient for the corresponding tap-weight multiplier. The most significant bit of the output of the higher significant bits is inverted and a group of bits is produced, each having the same binary value as the inverted most significant bit.

Abstract: A frame pattern inserter inserts a frame pattern generated by a frame pattern generator periodically into a signal to be transmitted. An echo canceling circuit generates a pseudoecho from the signal to be transmitted with the frame pattern inserted therein and an error signal. A timing controller extracts from a received signal a timing signal to control the frame pattern generator, the frame pattern inserter, and the echo canceling circuit, and outputs a phase signal indicating whether jitter of the timing signal is generated as a leading phase shift or a lagging phase shift. A jitter echo canceling circuit generates a pseudojitter echo from the error signal and the phase signal. The timing controller controls the timing signal to cause the jitter to be generated immediately after the frame pattern is inserted into the signal to be transmitted.

Abstract: Measurement of the successive levels of a received signal is achieved by combining together the elements of groups of digitized samples (E1 to Em) which are taken from the signal during successive sampling windows (W) positioned by a local clock (H) kept thoroughly synchronous with the signal. The combination consists of a weighted average so as to take account of the transmission conditions: passband of the channel, required flow rate, background noise, etc, likely to distort the signals transmitted and therefore to lead to errors in the measurement of the actual levels thereof. Such weighting is achieved by using the set of digital samples (E1 to Em) corresponding to a single group, for addressing a memory (10) in which the values to be selected for each one of the digital words have been previously stored.

Abstract: An interference canceler comprises an adaptive equalizer, first and second diversity branches, and an auxiliary branch. A first correlator detects a correlation between the output of the equalizer and the output of the first diversity branch, and a second correlator detects a correlation between the equalizer output and the output of the second diversity branch. The first and second diversity branch signals are multiplied with the detected first and second correlations, respectively, and diversity combined. A phase variation component of one of the first and second correlations is detected and multiplied with the output of the auxiliary branch to produce a signal whose phase rotation is the same as that of the diversity combined signal. A weight control signal is derived by detecting a correlation between a decision error of the adaptive equalizer and the multiplied auxiliary branch signal.

Abstract: A method and apparatus for improving the reliability of resynchronization in a serial frame based protocol communication system which can avoid resynchronization when line loss erroneously causes data to appear as a redundant unique code pattern. The synchronization is only initiated if two such unique code pattern bytes are received within a specified time separation.

Abstract: In a system where 2-level modulation and 4-level modulation of communication signals exist, an apparatus (107) demodulates either modulation scheme by demodulating (301) a received signal under the presumption that it is a 4-level signal, and if the received signal is detected (309) to be a 2-level signal, the signal is then demodulated (319) as a 2-level signal.

Abstract: A compensation circuit for adjusting the gain or loss of a four to two wire hybrid circuit in a telephone system automatically, regardless of the length of the telephone line interconnected to the hybrid circuit. The compensation circuit includes a converter, interface, gate array, and controller. The converter, which includes an amplifier with a variable gain, is connected to a digital carrier transmission line. The converter accepts a digital data signal and converts it to an analog intermediate signal. The interface receives the analog intermediate signal and transmits an analog telephone signal, along a customer loop telephone line, to a telephone. The interface also includes a pulse width modulated power converter for which the pulse width varies according to the length of the telephone line between the compensation circuit and the telephone. The gate array senses the pulse width and responsively provides a measured signal to the controller.

Abstract: The invention relates to an apparatus which is desiged for underground use in order to facilitate a two-way communication. The apparatus is operated within the frequency band 0.1-2 MHz, in order to make the electromagnetic waves propagate advantageously by utilizing the metal structures installed in the underground facilities and the bedrock itself. According to the invention, the transmitter/receiver unit is provided with an analog to digital converter (5) and respectively a digital to analog converter (20) in order to transmit the intermediate signal coded in digital form in between the two units of the apparatus.

Abstract: Synchronization is provided between a mobile radio station and a base station in a digital radiomobile system TDMA where the base station transmits a timeslot containing a preset frequency sinusoid. The method samples (according to different embodiments) the baseband demodulated signals and measures the phase increases between two subsequent samplings. Increases are compared with an intermediate threshold value between 0.degree. and 180.degree. to construct a vector formed by a series of values, the current sum of which is calculated. The minimum value of this sum is then identified to approximately synchronize the mobile station with the timeslot containing the sinusoid. Afterwards, the frequency offset between the local oscillator frequency and the base station oscillator frequency is calculated and corrected in order to correctly identify the timeslot containing the preamble for fine synchronization. Then the decoding of the message containing the station and the frame data is performed.

Abstract: A method of detecting the identity of a radio channel and to ascertain whether the channel is a control channel or a traffic channel, in conjunction with convolution decoding in a mobile radio receiver. Channel identification is effected without such complete decoding. Part of a data block is decoded in accordance with the Viterbi algorithm as though the block represented a control channel. If the metric obtained after a given number of nodes is smaller than a given number of threshold values, the channel is considered to be a control channel and is thereafter decoded as such a channel. If the metric is greater than the threshold value, the channel is decoded as a speech channel.

Abstract: A method and apparatus for demodulating data symbols transmitted through a fading communication channel. A plurality of first predetermined data symbols, a plurality of unknown data symbols, and a plurality of second predetermined data symbols are sequentially received. The received pluralities of data symbols are stored, and first and second sets of reference signals from the stored pluralities of first and second predetermined data symbols, respectively, are determined. The stored unknown data symbols based on the first set of reference signals are forward-demodulated, beginning with unknown symbols received nearer the first predetermined data symbols. The stored unknown data symbols based on the second set of reference signals are backward-demodulated, beginning with the unknown data symbols received nearer the second predetermined data symbols. Quality values indicative of demodulation qualities of the forward- and backward-demodulated data symbols are determined.

Abstract: A buffer memory, in which a first signal is written and from which a second signal is read out, and a subtractor which forms the difference between the counts of a read counter and a write counter, which control reading and writing. A justification decision circuit generates a stop signal for the read counter. An accumulator accumulates the difference signal over a predetermined time interval. The accumulator output, delayed by a time interval and weighted with a second factor, and a justification signal denoting the number of stuff bits caused by the justification decision circuit between two stop instants, are added to the subtractor output in the accumulator.

Abstract: A decimation filter for converting a received train of sigma-delta pulses in synchronism with a sigma-delta clock (fs) into a train of Pulse Code Modulation (PCM) samples having a PCM clock in accordance with the formula ##EQU1## includes a computer for computing one PCM sample from a sequence of sigma-delta samples in synchronism with the PCM clock and also a comparison circuit for determining whether phase correction of the PCM clock is necessary to lock the generation of the PCM samples on the sigma-delta clock extracted from the received sigma-delta signal, the decimation filter including shifters which shift the computation process at least one sigma-delta clock pulse in order to provide phase control in the generation of the PCM samples.

Abstract: Disclosed is a pulse detector that uses four samples of an analog signal to detect a pulse as soon as one sample beyond the time of the peak of the signal level at the pulse. The pulse detector can detect pulses by sampling at the center of a peak of the pulse or by sampling at either side of the peak of the pulse. The pulse detector detects pulses while tracking data, and it uses an alternate detection system for detecting pulses while acquiring timing and gain lock on a signal having a known data pattern. The detector uses either the sampled signal levels directly, or a moving average of two samples to perform the detection.

Abstract: A circuit and method for generating drive signals having a frequency synchronized to a reference frequency signal is disclosed. The circuit includes a PLL that includes a motor, and a circuit for generating a signal having a frequency proportional to the speed of the motor. A phase detector produces a signal for a time proportional to a phase difference between the motor speed signal and a reference frequency signal. A first phase difference measuring circuit produces a first voltage output signal at a first gain proportional to the phase difference when the duration of the phase detector signal is less than a predetermined time. A second phase difference measuring circuit produces a second output signal at a second gain when the duration of the phase detector signal is greater than the predetermined time. The first and second output signals are summed and applied to control the speed of the motor.

Abstract: A digital data radio transmission system for reproducing pre-velocity-modulation input frame data from the radio frame data subjected to velocity modulation and pulse insertion. The system includes a write counter that divides write clock pulses under control of frame position pulses to output write pulses; an elastic memory that temporarily stores the input frame data and the frame position pulses as per the write pulses; and a timing pulse generator that outputs control pulses in response to the supply of read clock pulses under control of the frame position pulses from the elastic memory. The system further comprises a read counter that divides the write clock pulses by the same number as with the division by the write counter to output read pulses; and a pulse inserting section that inserts pulses into the output frame data read from the elastic memory as per the read pulses to generate the radio frame data.

Abstract: A phase detector circuit, used in a very high frequency phase-locked loop, receives an incoming NRZI data stream and a phase-locked loop clock signal. For each data transition in the received data stream, the phase detector produces proportional phase error information in the form of two pulse signals PD1 and PD2. Pulse signal PD1 has a pulse width TW1 which corresponds to the amount and direction of any phase error between the data signal transition and the PLL clock signal. Pulse signal PD2 has a fixed width TW2 equal to half the period of the PLL clock signal. The phase detector also generates a recovered data signal and a recovered clock signal using identical parallel circuits so that the recovered signals are time synchronized. Furthermore, the recovered data signal is derived from signals in the phase error detection path, eliminating the need for two distinct circuits for data recovery and clock recovery.