Abstract: A receiver for receiving data signals which include data symbols C(k) having a symbol Baud rate. A local oscillator generates a local Baud rate clock for sampling a received signal, a symbol detector recovers the symbols C(k) from the signal samples, and an arithmetic processor circuit derives for each sample an error signal e(k) which is a measure of the phase difference between the local Baud rate clock and the symbol Baud rate clock of the received signal. A reference circuit generates a reference signal V.sub.r (k) which is proportional to the amplitude of the received symbols. The receiver further includes a control circuit (11) for forming from the signals C(k), e(k) and V.sub.r (k) a pair of control signals .DELTA.F and .DELTA..phi. which adjust the frequency and phase of the clock oscillator so as to reduce the aforesaid phase difference.

Abstract: In order to detect the format of asynchronously, serially transmitted character data using a command signal which includes a plurality of command character data, wherein the beginning of each of the command character data is identified by a start bit, and the character length of each of the character signals is L (a positive integer), the start bit is detected and a train of pulses generated to enable each of the character data to be sampled; the character signal is sampled and converted into a corresponding parallel signal; each of the parallel character signals outputted are ascertained; the number of character data received is counted and it is determined if a predetermined matching is achieved.

Abstract: A transceiver has a transmitter portion using serially coupled FETs coupled o low level positive and negative bias sources to enable a low power drain conversion of TTL input signals to low level serial data output signals for a coaxial data transmission cable and vice versa The transceiver also provides a constant 50 ohm impedance for the coaxial or triaxial transmission cable during active transmission periods, stand-by periods and power-off periods to provide an inexpensive method to transmit and receive 10 Megabit coded data via a coaxial or triaxial cable.

Abstract: A digital video quantizer for use in TCAS and ATCRBS/SIF systems. A digital delay receives a digitized video signal and produces a plurality of delayed digital signals which are used throughout the quantizer. A threshold generator then produces a predetermined threshold and a dynamic threshold, and a quantized video generator compares one of the delayed digitized signals to a threshold to produce a quantized video signal. A slope quantizer detects a slope of the digitized signal which exceeds either a positive or negative threshold. In addition, a rise time detector detects an excessive rise time in the digitized video signal, and a chip amplitude comparator provides a signal which is used in detecting Mode S data bit values. The digital video quantizer's use of digital references rather than analog references, eliminates the inaccuracies caused by a reference voltage varying over time or temperature. The digital references also facilitate modification of the reference values at a later time.

Abstract: In a communications network having time-dispersed signals, there is provided a mechanism for soft decision decoding. It comprises: radio reception of a time-dispersed signal, at least partly equalizing those time-dispersal effects, recovering information contained in the signal, multiplying with that recovered information the absolute value of that at-least-partly-equalized signal (scaled by a number derived from channel conditions over a time during which at least part of the information to be recovered is distributed), and error-correcting the multiplied information by a Viterbi algorithm channel decoding scheme of error correction. Accordingly, soft decision information is generated from within the equalization process itself.

Abstract: There is disclosed a local oscillating device useful for a communication system where frequency conversion is implemented to data signals received in a burst manner, particularly for INMARSAT STC-C (International Maritime Satellite Organization Standard - C) system.

Abstract: A communication system provides data packet timing alignment to facilitate soft handoff. A vocoder (315) transmits compressed voice frames to base-stations (130,131) along links (110,112) of variable length, .DELTA..sub.L. The .DELTA..sub.L translates to a delay .DELTA..sub.t in the air-frames to be transmitted by the base-stations (130,131). To compensate for the time delay .DELTA..sub.t, the communication system advances both sets of air-frames to be transmitted by base-stations (130,131) by at least .DELTA..sub.t so that skipping of frames, relative to an air-frame reference (300), during transmission does not occur.

Abstract: A method and apparatus are disclosed whereby a received signal comprising a binary spreading-code sequence, which belongs to a set of binary spreading-code sequences available to a transmitting node of a multi-node communication network, can be analyzed to determine the particular sequence from the set of sequences available to the transmitting node that was actually transmitted. All sequences of the set of available sequences have the property that each sequence can be generated by the same configuration of two linear feedback binary shift registers, where the feedback taps on the two binary shift registers correspond to primitive polynomials of the same degree over GF(2), the field of two elements. The received signal is correlated with each sequence of the set of available sequences to obtain a set of correlation values. The correlation values having the largest and the next-largest magnitudes are compared, and if their ratio exceeds a predetermined threshold, a detection decision is made.

Abstract: Clock timing is extracted from N level, multilevel codes of megabits per second data by determining a baud clock among the N-1 possible clocks synchronized to all the level cross points. A discriminator is used with a clock and if correct information is not obtained, the clock is changed.

Abstract: A digital transmission circuit for processing and outputting a digital output signal includes a mark density detecting circuit for detecting the amplitude of the DC signal component of the digital signal and a DC level shifter superposing a DC signal component on the digital signal in response to the detected amplitude. Thereby, the output signal level, regardless of the mark density of the input signal, does not drift.

Abstract: A device (400) and method (1200) include interleaved trellis precoding to provide a low probability of error in the presence of bursty noise. The use of interleaving and shaping, particularly in a trellis precoded system, provide for improved burst error bit correction.

Abstract: A method of recovering an original digital signal, after pulse stuffing, with reduced waiting time jitter. The original digital signal is written into a first elastic memory in a synchronizer. A pulse stuffed output of the synchronizer is transmitted to a desynchronizer where bits of the original signal are written into second elastic memory. Average values of fill levels of elastic memories in a synchronizer and in a desynchronizer are determined. The average value determined in the synchronizer is transmitted to the desynchronizer where a comparison of the respective average values is made in a comparator. A clock signal generating circuit in a phase locked loop is controlled by an output signal of the comparator so as to generate a clock signal. The signal bits written into the second elastic memory are read out of the second elastic memory at the rate of the generated clock signal.

Abstract: An improvement in an apparatus which uses a carrier detection threshold level for detecting a carrier signal modulated with binary data. The threshold level is dynamically changed and generally seeks a level above the background noise. The threshold level is maintained constant when the detected signal exceeds the threshold level. An evaluation circuit is able to examine the detected signal to determine whether it contains data or only noise, and if it contains only noise, a possible trapped condition is avoided by raising the threshold level to a level higher than the background noise.

Abstract: A method is provided for eliminating hold time violations in implementing high-speed logic circuits specified in circuit configuration data includes the steps of providing a synchronizer flip-flop device or latch corresponding to every flip-flop device or latch specified in the circuit configuration data. The synchronizer flip-flop is provided immediately upstream in the data path from its corresponding original user flip-flop device. A predetermined amount of delay is added to the user's original clock and data signals. A synchronizing clock signal generator provides a delayed synchronizer clock for each master clock in the circuit which is provided to each user flip flop.

Abstract: A phase-locked loop circuit and method for producing an output signal which is phase locked with respect to an input signal are disclosed. The circuit includes a phase detector responsive to the phase relationship between the input signal and the output signal. A controlled signal generator, which includes a voltage controlled oscillator, generates the output signal and includes coarse adjust circuitry and fine adjust circuitry. The coarse adjust circuitry causes the frequency of the output signal to fall within one of a selected group of frequency bands in response to the frequency of the input signal. Once the coarse adjustment is made, the fine adjust circuitry continuously changes the frequency and phase of the output signal in response to the phase detector so that the output signal will be phase locked to the input signal.

Abstract: A system for digital communication over a wire lain along the path of guided vehicles to a modem and a loop driver, the modem providing high frequency signals and the loop driver providing low frequency control signals. Instead, the modem and the loop driver are connected to one end of the wire and the other end of the wire is connected through an impedance matching network to earth ground. The impedance matching network provides an impedance approximately equal to the impedance of the wire at the frequency of the high frequency signals. The impedance matching network may conveniently comprise an inductor (choke) in parallel with a capacitor connected between the end of the wire and earth ground and a plurality of resistors connected in parallel with said inductor and capacitor. The resistors are selectively clipped to eliminate the echo bringing the impedance of the impedance matching network to approximate equality with the impedance of the wire at the frequency of the high frequency signals.

Abstract: A high-speed long-line data interface is provided which employs two pre-configured parallel connectors coupled by four lines. One connector is a convert/transmit connector and the other is an unconvert/receive connector. Each connector includes a processor which buffers incoming data. The four lines include an RS-422 pair of differential transmission lines, an RS-232 status line and a ground line. Incoming parallel data is converted to serial format, then transmitted over the differential transmission lines to the unconvert/receive connector. The serial data then is unconverted back to parallel format and output to the peripheral device. Status information is sent from the peripheral to the host computer over the status line as a multi-byte pulse encoded signal. Power for the convert/transmit connector is derived parasitically from the unconvert/receive connector via the status line. Storage capacitors store charge from the status line for driving the connector during a status transmission.

Abstract: In order to effectively reduce a memory size of each of two memories provided in an arrangement for converting a binary input data into the corresponding inphase and quadrature signals, a memory output controller and a sequential logic are provided. The memory output controller includes two polarity control circuits and two input data selectors. The two polarity control circuits are respectively coupled to the two memories, while the two input data selectors are preceded by and coupled to both of the two polarity control circuits. Each of the two polarity control circuits reverses the polarity of the output of the associated memory according to the output of the sequential logic. On the other hand, each of the two input data selectors is arranged to selectively acquire the outputs of the two polarity control circuits depending on the output of the sequential logic.

Abstract: A received time division multiple access (TDMA) signal having a time slot comprised of a plurality of symbols including at least one sequence of synchronizing symbols and a plurality of data symbols is demodulated by adaptively filtering the received signal to minimize inter-symbol interference due to an effect of channel signal propagation delay. The adaptive filtering step is performed by processing the received signal with a multi-stage lattice decision feedback equalizer having (M=N.sub.1 -N.sub.2) stages followed by (N.sub.2 -1) two-dimensional stages. A metric is next formed for each of the stages in accordance with a predetermined mathematical relationship between the output signals of each of two stages. A plurality of the formed metrics are next accumulated over a plurality of time slots.

Abstract: A device is capable of electronically reversing the polarity of a polarized data link interface used between a data termination equipment (DTE) and either a data communication equipment (DCE) or another data termination equipment (DTE). In this manner, the establishment of physical level connectivity in the data link interface is simplified and the interfacing of DTEs (such as computers) and peripheral devices is improved.