Abstract: A system is provided implementing an extremely high speed link allowing selection of either twisted pair (or like media) and fiber media in to provide a high speed multimedia local area network. A high speed transmission link for twisted pair, coaxial cable media or the like includes a transmitter with a conversion device for receiving fiber optic data interface signals intended to drive a fiber optic data interface and for converting these fiber optic data interface signals into high speed transmission link signals of a form suitable to drive a twisted pair medium. A receiver is provided and includes a reconversion device for regenerating the signal received from the twisted pair medium back to an adequate signal level. The transmitter conversion device includes a buffer cooperating with an equalizer and a filter for forming the high speed transmission link signal. The equalizer provides frequency domain compensation for the characteristics of the twisted pair medium.

Abstract: A coherent demodulating device is characterized by a demodulating circuit and a carrier recovering circuit produced entirely in digital form. Two quadrature demodulation carrier waves produced by a local oscillator are mixed with a demodulation carrier signal modulated by symbols to produce analog signals. The analog signals are digitized by sampling at symbol reception frequency into incoming digital signals. A digital phase shifter phase shifts the incoming signals by a demodulation phase derived by a phase loop digital processing circuit as from error signal pulses supplied by a comparing circuit receiving outgoing digital signals from the phase shifter. The compensation for the phase and frequency differences between the demodulation and modulation carrier waves is carried out a posteriori in digital form by phase shifting the incoming signals.

Abstract: A decoder for reproducing information from an encoded signal that has been frequency-domain transformed by a transform conversion circuit in response to audio signal samples grouped into time-domain blocks based on selected block time lengths, includes a reverse conversion transformation circuit that groups the frequency-domain transfer coefficients into transform blocks based on the block time length information used in the encoding operation and applies the inverse discrete transform function to generate time-domain signal sample blocks therefrom.

Abstract: A signal encoding apparatus for cutting out blocks of an input signal waveform at a predetermined time interval and converting the in-block signal by mutually independent conversion axes for encoding, wherein the waveform cutting block length along the time axis is changed according to the input signal.

Abstract: A system for encoding audio signals, transmitting or recording the encoded audio signals, and then decoding the transmitted audio signal includes a circuit for determining the block length of the input audio signals based upon detected values of predetermined portions of the input signal and then performing an orthogonal conversion of the determined block length signal, in which the signal is orthogonally transformed from a time-domain signal to a frequency-domain signal. Following quantization, the converted and encoded signal is transmitted and upon performing reverse quantization, a reverse orthogonal converting circuit converts the signal back to the time-domain in keeping with the signal providing information concerning the various block lengths that were determined during encoding. The converted time-domain signals are then connected into a smooth waveform to form output audio signals.

Abstract: A method for improving time synchronization of digital data signals in receivers by using more than one known data sequence to provide a plurality of timing recovery functions and based on these, one or more optimal sampling points. By using existing data sequences in each frame, the disclosed method provides improved time synchronization without increasing transmission overhead.

Abstract: A method and apparatus provide a noise detector generating a logic output indicating presence of noise in an incoming signal and an attenuation controller for providing a stepped-response to noise operatively connected to respond to the logic output to record a count of noise detections.

Abstract: Optimal baud rate and carrier frequency for data transmission using a modem on a communication channel (100) are determined by utilizing an on-line line probing technique. The technique utilizing the information from a decoder noise power spectrum estimated from the equalized received modulated signals and decoder output symbols to determine the decoder signal-to-noise ratios (SNRs) and supported bit rates for the available baud rates and carrier frequencies. These SNRs and bit rates together with a band edge SNR difference at each frequency band are utilized to select (110) the optimal baud rate and carrier frequency.

Abstract: This invention relates to an equalizer for equalization of a linear modulated signal received in blocks or frames over a radio channel. The impulse response of the channel is estimated during training sequences before and after a frame and interpolation is used to estimate the impulse response at each point in the frame. From this, the coefficients of an equalizer (24, 26) are calculated for equalising the signal. Various further improvements are described. The technique is particularly applicable to land mobile radio systems using 16 QAM or other linear modulation schemes.

Abstract: The device serves to interconnect first and second sections of a data bus in order to provide a transparent bi-directional data transmission along the bus comprised of the two sections, irrespective of the protocol used. Basically, the device includes a first transmitter-receiver module at which terminates a first bus section, and a second transmitter-receiver module at which terminates a second bus section. Both modules are disposed face-to-face without contact and are electromagnetically coupled. Each receiver module has a circuit for supplying a transmitting coil with a signal modulated by the data to be transmitted and coming from the bus section to which the module is connected, and a detector circuit for receiving a modulated signal from the same coil to produce the data to be transmitted to the bus section to which the module is connected.

Abstract: A digital decision feedback equalizer utilizes a finite impulse response (FIR) filter and an infinite impulse response (IIR) filter in parallel in the feedback path. The FIR filter compensates for the rapidly changing region of the channel impulse response immediately following the cursor while the IIR filter compensates for the gradually decaying tail of the impulse response of the channel. Modifications of a sequential identification algorithm are used to adapt the filter sections. In particular, in one modification, the inputs to both the poles and zeros sections of the IIR filter are prefiltered by an all-pole filter, where the poles of this filter are the current pole estimates. In another modification, the order of the zeros section of the IIR filter and the all-pole filter are reversed, and the zeros section is adapted using the least mean squares algorithm. A recursive least squares algorithm with exponential fading can be used to adapt the poles and/or zeros section of the IIR filter.

Abstract: Linking of radio paging transmitters is accomplished through the utilization of TDM transmission on the same channel as that assigned to the paging service, thus eliminating the necessity of a separate channel for linkage of the remote transmitting sites to a central originating location. For data transmission, real time data is broadcast via a direct RF link to buffer storage at each of the remote transmitting sites, with the data being read out to each of the paging transmitters from the local buffers in a phase-adjusted synchronized fashion under control of sync signals generated at and broadcast from the central originating location. The data transmission rate from the central originating location to the remote sites may be made significantly higher than the radio paging data rate in order to minimize link time to minimize linkage overhead by reducing the amount of time the channel is used for linkage as opposed to paging.

Abstract: A fundamental period calculation circuit calculates a fundamental period in accordance with a plurality of pulses including reproduction target pulses included in binary reproduced output signal pulses sequentially input as digital signal pulses to be reproduced. A clock generator generates a demodulation clock having the fundamental period calculated by the fundamental period calculation circuit. A phase error amount detecting circuit detects a phase error amount in accordance with a phase difference between the demodulation clock generated by the clock generator and a plurality of pulses including the reproduction target pulses. A synchronizing circuit controls the phase error amount of a generation timing of the demodulation clock by the clock generator to a predetermined value in accordance with the phase error amount detected by the phase error amount detecting circuit so that the demodulation clock generated by the clock generator is synchronized with each of the reproduction target pulses.

Abstract: A reference voltage (V.sub.ref) is set to a received signal level corresponding to an anticipated data error rate and compared with outputs of intermediate frequency amplifiers (3-1, 3-2) by comparators (7-1, 7-2). When the outputs of the intermediate frequency amplifiers (3- 1, 3-2) are lower than the reference voltage (V.sub.ref), operation of receiving circuits (A12-1, B12-2) is stopped. At inter symbol interference amount calculating sections (6-1, 6-2), inter symbol interference amounts are calculated from auto-correlation parameters of preamble signal bit trains included in received signal data, and selectors (9-1, 9-2) are controlled so that a diversity branch having the least residual inter symbol interference amount or the highest S/N ratio is selected and the received signal data of the selected branch are inputted to an equalizing section (11). When a signal having a high data error rate is received, operation of the corresponding receiving circuit is stopped.

Abstract: The present patent application discusses a frequency translation apparatus for altering the effective frequency of the phase information of an input signal (115). The input signal (115) has a first phase (.theta.(t)) and a first frequency (f.sub.i). The phase of the input signal is extracted and digitized at a second frequency (f.sub.o), forming a second N-bit digital phase signal (.theta.'(t))(311). The frequency translation apparatus generates a third digital phase signal (319) which approximates the difference between .theta.(t) and .theta.'(t). Then, the frequency translation apparatus combines the second digital phase signal and the third digital phase signal, forming a fourth digital phase signal (307) substantially approximating the first phase signal.

Abstract: A frame alignment circuit is disclosed which includes multi-stage dividing counters and multi-stage line demultiplexing circuits. The shift pulse for frame synchronizing is converted to the width of the first divided clock signal and applied to the first dividing counter. Accordingly, the frame synchronization is easily established by demultiplexing the high rate multiplexed coded signal even if the number of demultiplexing line is increased.

Abstract: In a decision-feedback equalizer for use in combination with a demodulator (13) to equalize a demodulated signal into an equalized signal through first and second transversal filters (15, 16), the demodulated signal and an input signal are filtered by the first and the second transversal filters into the first and the second filtered signals in accordance with a plurality of main controllable tap gains and a plurality of subsidiary controllable tap gains, respectively. The input signal supplied to the second transversal filter is controlled or selected by a supplying circuit (42). Specifically, the supplying circuit (42) produces as the input signal a first local signal obtained from the demodulated signal when the demodulator is put in a synchronization state. The supplying circuit produces as the input signal a second local signal obtained from the equalized signal when the demodulator is put out of the synchronization state.

Abstract: A TDMA RF received signal is demodulated by first being filtered with a fixed transversal filter having a characteristic selected for matching a fixed square root raised cosine pulse characteristic of the received signal. The filtered signal is then adaptively filtered for compensating for a time varying impulse response of the channel. The adaptive filtering is performed initially during a synchronizing portion (preamble) of the filtered signal in accordance with a fast recursive least squares algorithm. Subsequent filter adaptation to a data portion of the filtered signal is accomplished in accordance with a computationally less expensive normalized least mean square procedure. The adaptive filter repetitively applies a modified Viterbi algorithm to blocks of 2D symbols, such that D symbols are released for adapting the adaptive filter means during the data portion of the filtered signal and the signal.

Abstract: A radio communication apparatus for transmitting and receiving a digital signal using a radio line which includes a memory means for storing a plurality of signal procedures in which each procedure has different ratio of the information code bits and error correction code bits.A signal processing circuit executes one of the procedures stored in the memory means according to line quality. Accordingly, the radio communication apparatus of the present invention selects the optimum procedure according to the line quality, and then reduces the consumed power.

Abstract: A phase lock loop circuit (10) which locks to a frequency within a range of input signal frequencies. A frequency discriminator (12) of phase lock loop circuit (10) determines a maximum pulse width of the input signal by counting a number of pulses of a reference signal in each of a series of pulses of the input signal. A coarse frequency controller (16) compares the maximum pulse width to two threshold values to determine whether the reference signal should be coarsely or finely adjusted. If the reference signal is coarsely adjusted, control circuit (16) provides a coarse frequency control signal to indicate whether a voltage controlled oscillator, VCO, (26) should increase or decrease the reference frequency. If the reference frequency is finely adjusted, a phase discriminator (22) provides a fine frequency control signal to the VCO to either increase or decrease the frequency of the reference signal with greater resolution.