Patents Examined by Young Whang
  • Patent number: 5367437
    Abstract: A mounting arrangement of the present invention is provided for packaging a plurality of multiple layer capacitors together. First and second coupling devices are coupled electrically to respective first and second electrodes of each multiple layer capacitor of the plurality of multiple layer capacitors. A clamping devices clamps the first and second coupling devices, the plurality of multiple layer capacitors, and an electrically insulating layer to a mounting surface so that the electrically insulating layer is between the first coupling devices and the mounting surface and so that the plurality of multiple layer capacitors are electrically connected in parallel between the first and second coupling devices.
    Type: Grant
    Filed: April 6, 1993
    Date of Patent: November 22, 1994
    Assignee: Sundstrand Corporation
    Inventor: W. Kyle Anderson
  • Patent number: 5367436
    Abstract: In a probe terminating apparatus, ground terminals, power supply terminals, and open terminals are provided on a print circuit board, and a ground potential applying terminal and a power supply voltage applying terminal are also provided on the print circuit board. In addition, a pull-down resistance apparatus is inserted to be connected between each of the ground terminals and the ground potential applying terminal, and a pull-up resistance apparatus is inserted to be connected between each of the power supply terminals and the power supply voltage applying terminal. Terminals of an evaluation microcomputer in an in-circuit emulator are connected to the ground terminals, the power supply terminals, and the open terminals by the connection of a probe and an IC socket, or connectors. The probe is connected to the terminals of the evaluation microcomputer, and the IC socket is connected to the ground, power supply and open terminals of the probe terminating apparatus.
    Type: Grant
    Filed: March 8, 1993
    Date of Patent: November 22, 1994
    Assignee: NEC Corporation
    Inventor: Satoshi Ikei
  • Patent number: 5367435
    Abstract: An electronic package and method of making same wherein a flexible circuitized substrate is used to interconnect contact sites on a semiconductor device (chip) to respective conductors on a circuitized substrate (PCB). Significantly, the flexible substrate is coupled to the PCB using solder elements which are applied to the flexible substrate prior to semiconductor device coupling to others of the flexible substrates' conductive elements. These other conductive elements are then connected to the devices' contact sites using thermocompression bonding, the bonding occurring through an aperture in the flexible substrate.
    Type: Grant
    Filed: November 16, 1993
    Date of Patent: November 22, 1994
    Assignee: International Business Machines Corporation
    Inventors: Frank E. Andros, Christopher G. Angulas, Joseph M. Milewski
  • Patent number: 5365402
    Abstract: A cooling apparatus for an electronic device of high calorific density including an elastomer interposed between a semiconductor chip and a heat sink so as to connect them thermally. The elastomer may also be in close contact with a large number of semiconductor chips having various configurations which are mounted on a board, so that the elastomer is thermally connected with them, whereby the elastomer absorbs thermal deformations.
    Type: Grant
    Filed: November 29, 1991
    Date of Patent: November 15, 1994
    Assignee: Hitachi, Ltd.
    Inventors: Toshio Hatada, Shigeo Ohashi, Tadakatsu Nakajima, Heikichi Kuwahara, Hitoshi Matsushima, Motohiro Sato, Hiroshi Inouye, Takao Ohba, Akira Yamagiwa, Kanji Otsuka, Yuuji Shirai
  • Patent number: 5365405
    Abstract: A multi-chip module has a carrier (21) of monocrystalline silicon whose surface is at least partially enlarged by anodic electro-chemical etching in a fluoride-containing acidic electrolyte. At least one capacitor (23) that has a dielectric layer and a conductive layer is arranged on the enlarged surface of the carrier (21), whereby the carrier (21) and the conductive layer act as capacitor electrodes.
    Type: Grant
    Filed: May 21, 1993
    Date of Patent: November 15, 1994
    Assignee: Siemens Aktiengesellschaft
    Inventors: Wolfgang Hoenlein, Volker Lehmann
  • Patent number: 5363279
    Abstract: A semiconductor package having outer leads which are not protruded from the package but only exposed to outside. The semiconductor package comprises a semiconductor chip which is formed with a plurality of bond pads at a central portion of its bottom surface, a lead frame including leads connected to bond pads for input/output of the bond pads respectively and bus bars connected to power supplying pads of the bond pads, insulation adhesives for attaching inner leads of the leads and inner leads of the bus bars to a bottom surface of the semiconductor chip formed with the bond pads, metal wires for electrically connecting the inner leads of the leads and the inner leads of the bus bars to the bond pads respectively, and a molding compound enveloping the semiconductor chip assembly with outer leads of the lead frame exposed to outside. The adhesive tapes are removed after a molding procedure.
    Type: Grant
    Filed: November 3, 1992
    Date of Patent: November 8, 1994
    Assignee: Goldstar Electron Co., Ltd.
    Inventor: Gi Bon Cha
  • Patent number: 5363277
    Abstract: The structure and method for mounting a semiconductor device, in which a wiring pattern 2 on a circuit substrate 1 and projection electrodes 5 of an integrated circuit 4 are made to be in opposition to and connected to each other, the wiring pattern 2 is connected to the projection electrodes 5 while penetrated through an adhesive and thermosetting thin film member 3 covering the wiring pattern 2; and the integrated circuit 4 is held onto the circuit substrate 1 by a hardening force of the adhesive and thermosetting thin film member 3.
    Type: Grant
    Filed: December 16, 1992
    Date of Patent: November 8, 1994
    Assignee: Rohm Co., Ltd.
    Inventor: Osamu Tanaka
  • Patent number: 5363282
    Abstract: Method of and construction for mounting a luminous bulb unit in the luminous body unit according to the present invention aims at simplifying the work of mounting a luminous simple to a support plate. By making the electric joining construction and connecting and fixing construction into a single construction, processes of mounting the luminous bulb unit and electric wiring are simplified, with the result of lower manufacturing cost.
    Type: Grant
    Filed: November 10, 1992
    Date of Patent: November 8, 1994
    Assignee: Teiryo Industry Incorporated
    Inventor: Yoshida Hirokazu
  • Patent number: 5355282
    Abstract: An object of the present invention is to provide a connector structure for achieving a signal connection between modules not by way of a motherboard. In an electronic apparatus in which a plurality of modules (3, 4) are mounted on a motherboard (1) in an orderly manner, while flatly positioned parallel to the latter, and electrical connections between the modules and between the respective module and the motherboard are achieved by a connector body (2) extending along a boundary between the adjacent modules (3, 4), contacts (6, 7) are provided in the peripheral regions of the respective module (3, 4). Both the contacts (6, 7) are electrically connected with each other by pressing a connector spring (8) fixed in the connector body (2) onto the contacts (6, 7) provided in the peripheral regions of the adjacent modules (3. 4).
    Type: Grant
    Filed: April 26, 1993
    Date of Patent: October 11, 1994
    Assignee: Fujitsu Limited
    Inventors: Hitoshi Yokemura, Masao Hosogai, Yuko Tsujimura
  • Patent number: 5353199
    Abstract: A method of mounting fuse holding clips for a fuse holder on a circuit board by such an automatic part inserter as is used for inserting radial parts and including a pusher having a lower dead point set at 5 to 20 mm upwardly distant from an upper face of the circuit board and comprising a step of inserting a fuse holding clip while the pusher of the automatic inserter is engaging narrowed faces of a clip body which are to support a lower portion of a fuse until a bottom of the fuse holding clip is engaged with the upper face of the circuit board.
    Type: Grant
    Filed: March 18, 1993
    Date of Patent: October 4, 1994
    Assignee: Kyoshin Kogyo Co., Ltd.
    Inventor: Kozi Ohashi
  • Patent number: 5353196
    Abstract: A method of assembling an electrical packaging structure has a plurality of semiconductor chips arranged on a substrate and input wirings to the semiconductor chips connected thereto. The input wirings are distributed through a wiring board arranged on the substrate.
    Type: Grant
    Filed: December 20, 1993
    Date of Patent: October 4, 1994
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masanori Takahashi
  • Patent number: 5353195
    Abstract: A multi-chip module includes a substrate supporting a plurality of chips. A dielectric layer which overlies the chips and the substrate has a connection surface and a substrate surface with metallization planes having plane openings patterned on each surface and vias aligned with predetermined pads on the chips and predetermined portions of the metallization plane of the substrate surface. An adhesive layer is situated between the substrate and the substrate surface of the dielectric layer, and a pattern of electrical conductors extends through the vias to interconnect selected chips and selected portions of the metallization planes. In a related design, the dielectric layer may be a board having chip openings and conductive through-connections aligned with predetermined portions of the metallization plane of the substrate surface.
    Type: Grant
    Filed: July 9, 1993
    Date of Patent: October 4, 1994
    Assignee: General Electric Company
    Inventors: Raymond A. Fillion, Robert J. Wojnarowski
  • Patent number: 5349500
    Abstract: An apparatus is described for electrically connecting flip chips to a flexible printed circuit substrate. The apparatus comprises (1) providing solder paste to a plurality of active contact pads located on the flexible printed circuit substrate, (2) placing the flip chips on the substrate such that solder bumps located on the flip chips are in registration with the solder paste on the active contact pads, and (3) heating the resulting assembly as a whole so that the solder paste on each active contact pad fellows to form an electrical connection with its corresponding solder bump.
    Type: Grant
    Filed: June 23, 1993
    Date of Patent: September 20, 1994
    Assignee: Sheldahl, Inc.
    Inventors: Keith L. Casson, Kelly D. Habeck, Eugene T. Selbitschka
  • Patent number: 5349501
    Abstract: An electronic device adaptive to mounting on a printed wiring board, which has outer leads that are not subject to be deformed by external force, which helps improve positioning precision when it is mounted, and which can be transported at a reduced cost. A plurality of conductor leads connected to an electronic circuit provided in the electronic device extend along a peripheral surface of the package, and at least the ends of the conductor leads are fixed to the peripheral surface of the package to constitute input/output terminals of the electronic circuit. Preferably, the conductor leads are formed on a flexible film, bent along the peripheral surface of the package together with the film and are fixed to a bottom surface of the package via the film. Preferably, furthermore, a film in the form of a tape is employed, and a plurality of packages are arranged and supported on the film while maintaining a predetermined distance between one another.
    Type: Grant
    Filed: October 9, 1992
    Date of Patent: September 20, 1994
    Assignee: Nippon Steel Corporation
    Inventor: Youji Kawakami
  • Patent number: 5347428
    Abstract: A computer module is disclosed in which a stack of glued together IC memory chips is structurally integrated with a microprocessor chip. The memory provided by the stack is dedicated to the microprocessor chip. The microprocessor and its memory stack may be connected either by glue and/or by solder bumps. The solder bumps can perform three functions--electrical interconnection, mechanical connection, and heat transfer. The electrical connections in some versions are provided by wire bonding.
    Type: Grant
    Filed: December 3, 1992
    Date of Patent: September 13, 1994
    Assignee: Irvine Sensors Corporation
    Inventors: John C. Carson, Ronald J. Indin, Stuart N. Shanken
  • Patent number: 5345366
    Abstract: A substrate to substrate interconnect and standoff assembly (10) comprises an electronic coupling (39) between the bottom of a first substrate (14) and the bottom of a second substrate (12), an electronic coupling (24) of the top of the first substrate to the bottom of the second substrate, a stand-off (20) between the first substrate and the second substrate, and a mechanical coupling (16) between the first substrate to the second substrate.
    Type: Grant
    Filed: May 21, 1993
    Date of Patent: September 6, 1994
    Assignee: Motorola, Inc.
    Inventors: Chee F. Cheng, Chiou C. You, Kai L. Tong
  • Patent number: 5345363
    Abstract: An integrated circuit package which utilizes a standard TAB tape that can couple a lead frame to one of a number of integrated circuit dies that have different outer dimensions. The TAB tape includes a sheet of polyimide which supports a plurality of conductive leads. The sheet has a rectangular center opening which provides clearance for the IC die. Adjacent to each edge of the center opening are a plurality of equally spaced contact openings which expose portions of the leads. The leads are coupled to the integrated circuit by attaching the contact portions to the surface pads of the die. The contact openings are located at various distances from the center opening so that the tape can accommodate different die sizes. The leads of the TAB tape are also attached to a lead frame through lead frame openings in the polyimide.
    Type: Grant
    Filed: April 7, 1993
    Date of Patent: September 6, 1994
    Assignee: Intel Corporation
    Inventors: Bidyut Bhattacharyya, Koushik Banerjee
  • Patent number: 5343363
    Abstract: Disclosed is a split backed pressure sensitive die carrier tape including a flexible carrier member having a plurality of holes formed therein of a size larger than a die to be carried. Two strips of pressure sensitive adhesive tape are placed along the back face of the carrier partially covering each hole in the carrier. The two strips of substantially straight pressure sensitive tape are spaced apart so that a poke up needle can be passed between the pressure sensitive tape and through the hole formed in the carrier without tearing or damaging either strip of pressure sensitive tape. An integrated circuit chip is positioned in the hole in the carrier and secured to the pressure sensitive tapes.
    Type: Grant
    Filed: December 21, 1992
    Date of Patent: August 30, 1994
    Assignee: Delco Electronics Corporation
    Inventors: Michael R. Greeson, James C. Baar, Jerry D. Haines, James J. Tepe
  • Patent number: 5339219
    Abstract: A modulated electronic breadboard assembly kit for constructing and testing prototype circuits. The kit includes a motherboard that has a plurality of connectors having leads that are connected to a plurality of corresponding pins. The leads between the various connectors can be coupled together by wires wrapped around the pins. The kit also contains a plurality of discrete modules which can be plugged into the connectors of the motherboard. The discrete modules each provide a basic electronic function such as an operational amplifier, an analog to digital converter, a comparator, etc. A prototype circuit can be built with the present invention by merely selecting the desired circuit functions, plugging the corresponding modules into the motherboard and then wiring the leads of the board to connect the modules.
    Type: Grant
    Filed: April 5, 1993
    Date of Patent: August 16, 1994
    Inventor: Alex Urich
  • Patent number: 5335146
    Abstract: A high density interconnection technique for connecting large numbers of unique signal lines between orthogonally positioned circuit cards, utilizes pins from the back of a zero insertion force connector (ZIF) to extend through the interconnection card and mate with a female socket connector on a second circuit board. Pins from the ZIF connector which are not aligned with the sockets of the orthogonally positioned socket connector may be connected to pins on the interconnection card which are aligned with the socket connector but not the ZIF. Very high numbers of connections between circuit cards may be made in a small volume and maintain signal line length at a minimum to ensure maximum signal transfer speed.
    Type: Grant
    Filed: January 29, 1992
    Date of Patent: August 2, 1994
    Assignee: International Business Machines Corporation
    Inventor: Robert F. Stucke