Abstract: A display device includes: a substrate comprising a display area and a peripheral area outside the display area; a first connection line in the display area, the first connection line comprising a first portion extending along a first column of the display area and in the first column, a third portion extending along a second column of the display area and in the second column, and a second portion connecting the first portion to the third portion; and a second connection line in the peripheral area and connected to the third portion of the first connection line and a data line in a third column of the display area.

Abstract: A method for producing a hybrid structure, the hybrid structure including at least one structured Majorana material and at least one structured superconductive material arranged thereon includes producing, on a substrate, a first mask for structured application of the Majorana material and a further mask for structured growth of the at least one superconductive material, which are aligned relatively to one another, and applying the at least one structured superconductive material to the structured Majorana material with the aid of the further mask. The structured application of the Majorana material and of the at least one superconductive material takes place without interruption in an inert atmosphere.

Abstract: A method of manufacturing an MRAM device, the method including forming a first magnetic layer on a substrate; forming a first tunnel barrier layer on the first magnetic layer such that the first tunnel barrier layer includes a first metal oxide, the first metal oxide being formed by oxidizing a first metal layer at a first temperature; forming a second tunnel barrier layer on the first tunnel barrier layer such that the second tunnel barrier layer includes a second metal oxide, the second metal oxide being formed by oxidizing a second metal layer at a second temperature that is greater than the first temperature; and forming a second magnetic layer on the second tunnel barrier layer.

Abstract: A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing planar devices. The GAA vacuum channel transistor features stacked, tapered source and drain regions that are formed by notching a doped silicon pillar using a lateral oxidation process. A temporary support structure is provided for the pillar during formation of the vacuum channel. Performance of the GAA vacuum channel transistor can be tuned by replacing air in the channel with other gases such as helium, neon, or argon. A threshold voltage of the GAA vacuum channel transistor can be adjusted by altering dopant concentrations of the silicon pillar from which the source and drain regions are formed.

Abstract: Metallization structures under a semiconductor device layer. A metallization structure in alignment with semiconductor fin may be on a side of the fin opposite a gate stack. Backside and/or frontside substrate processing techniques may be employed to form such metallization structures on a bottom of a semiconductor fin or between bottom portions of two adjacent fins. Such metallization structures may accompany interconnect metallization layers that are over a gate stack, for example to increase metallization layer density for a given number of semiconductor device layers.

Abstract: The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component.

Abstract: An organic light emitting diode display device, including a flexible substrate; pixels on the flexible substrate, the pixels including an organic emission layer; a pixel definition layer between the pixels, the pixel definition layer including openings; an encapsulation layer covering the pixels; and a conductive light shielding member on the encapsulation layer, the conductive light shielding member not overlapped with the pixels, and overlapped with the pixel definition layer.

Abstract: A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench.

Abstract: It is disclosed to obtain a frequency transformed radiomap data set by applying a discrete frequency transform to an original radiomap data set. It is also disclosed to obtain a reconstructed radiomap data set by applying an inverse discrete frequency transform to a frequency transformed radiomap data set.

Abstract: A semiconductor package according to the inventive concept includes a first semiconductor chip configured to include a first semiconductor device, a first semiconductor substrate, a plurality of through electrodes penetrating the first semiconductor substrate, and a plurality of first chip connection pads arranged on an upper surface of the first semiconductor substrate; a plurality of second semiconductor chips sequentially stacked on an upper surface of the first semiconductor chip and configured to each include a second semiconductor substrate, a second semiconductor device controlled by the first semiconductor chip, and a plurality of second chip connection pads arranged on an upper surface of the second semiconductor substrate; a plurality of bonding wires configured to connect the plurality of first chip connection pads to the plurality of second chip connection pads; and a plurality of external connection terminals arranged on a lower surface of the first semiconductor chip.

Abstract: An image sensing device includes a first pixel array and a second pixel array. The first pixel array includes a plurality of first unit pixels consecutively arranged to generate a first pixel signal through a photoelectric conversion of incident light. The second pixel array is disposed below the first pixel array, and includes a plurality of second unit pixels consecutively arranged to generate a second pixel signal through a photoelectric conversion of the incident light. The first unit pixels are arranged to have a uniform spacing between adjacent first unit pixels in the first pixel array. The second unit pixels are arranged so that spacing between adjacent second unit pixels are not the same in the second pixel array.

Abstract: This patent application relates to microelectronic device packages with internal EMI shielding, methods of fabricating and related electronic systems. One or more microelectronic devices of a package including multiple microelectronic devices are EMI shielded, and one or more other microelectronic devices of the package are located outside the EMI shielding.

Abstract: An integrated circuit (IC) package includes a first die with a first surface overlaying a substrate. The first die includes a first metal pad at a second surface opposing the first surface. The IC package also includes a dielectric layer having a first surface contacting the second surface of the first die. The IC package further includes a second die with a surface that contacts a second surface of the dielectric layer. The second die includes a second metal pad aligned with the first metal pad of the first die. A plane perpendicular to the second surface of the first die intersects the first metal pad and the second metal pad.

Abstract: A stack package is disclosed. A first semiconductor die and a supporter are disposed on a package substrate. The supporter may include a second side facing a first side of the first semiconductor die having a substantially inclined surface. A second semiconductor die is stacked on the first semiconductor die and on the supporter. An encapsulant layer is formed to fill a portion between the supporter and the first semiconductor die.

Abstract: In some examples, a semiconductor package comprises a semiconductor die; a conductive member coupled to the semiconductor die; and a wirebonded protrusion coupled to the conductive member. A physical structure of the wirebonded protrusion is determined at least in part by a sequence of movements of a wirebonding capillary used to form the wirebonded protrusion, the wirebonded protrusion including a ball bond and a bond wire, and the bond wire having a proximal end coupled to the ball bond. The bond wire has a distal end. The package also comprises a mold compound covering the semiconductor die, the conductive member, and the wirebonded protrusion. The distal end is in a common vertical plane with the ball bond and is not connected to a structure other than the mold compound.

Abstract: The present application describes a system in package which features no printed circuit board inside an encapsulation structure and comprises: a copper holder with a silicon layer at a top face; a plurality of dies mounted on the silicon layer and electrically connected to a plurality of data pins of the copper holder; a passive element mounted on the silicon layer and electrically connected to the dies wherein the dies are electrically connected to the ground pin of the copper holder; a molding compound encasing the dies and the passive element on the top face of the copper holder.

Abstract: A semiconductor package includes a package substrate including an insulating layer having an upper surface and a lower surface and provided with a first region which is recessed to a first depth from the upper surface toward the lower surface, a redistribution wiring buried in the insulating layer, a chip connection pad on a bottom surface of the recessed first region and connected to the redistribution wiring, and a wire connection pad on the upper surface of the insulating layer and connected to the redistribution wiring, a first semiconductor chip overlapping, in a top-down view of the semiconductor package, the recessed first region of the insulating layer and comprising a first chip pad connected to the chip connection pad of the package substrate, and a second semiconductor chip on the first semiconductor chip and connected to the wire connection pad of the package substrate through a conductive wire.

Abstract: A display device includes a display device including a substrate, and a display unit disposed on the substrate. An encapsulating unit encapsulates the display unit. The encapsulating unit includes a barrier organic layer. The barrier organic layer includes a plurality of organic materials and a plurality of inorganic materials. The inorganic materials are arranged in free volumes between the organic materials.

Abstract: A semiconductor package includes a package substrate, a processor chip mounted on the package substrate, a first stack structure on the package substrate, the first stack structure including a number M of memory chips stacked on the processor chip, and a second stack structure on the package substrate and spaced apart from the processor chip, the second stack structure including a number N of memory chips stacked on the package substrate. A number Q of channels that electrically connect the memory chips of the second stack structure with the processor chip may be greater than a number P of channels that electrically connect the memory chips of the first stack structure with the processor chip, or the number N of memory chips included in the second stack structure may be greater than the number M of memory chips included in the first stack structure.

Abstract: A power module includes a plurality of conductive wire groups and a sealing member. The plurality of conductive wire groups each include a first bonded portion and a second bonded portion. A maximum gap between intermediate portions of a pair of conductive wire groups adjacent to each other is larger than a first gap between the first bonded portions of the pair of conductive wire groups adjacent to each other. The maximum gap between the intermediate portions of the pair of conductive wire groups adjacent to each other is larger than a second gap between the second bonded portions of the pair of conductive wire groups adjacent to each other. Therefore, the power module is improved in reliability.