Abstract: A semiconductor package structure includes a substrate, including first conductive pads and packaging pads opposite to the first conductive pads, one or more semiconductor chips stacking on the substrate, a molding compound encapsulating the semiconductor chips, first metal wires connecting the semiconductor chips to the packaging pads, a first metal pad on a side of the molding compound opposite to the substrate, and a second metal wire located in the molding compound and connecting the first metal pad to a chip-contact pad of a semiconductor chip of the semiconductor chips.

Abstract: An image sensor includes a color filter array, a first photoelectric conversion device configured to absorb first light passing through the color filter array and convert the absorbed first light into electrical signals, and a second photoelectric conversion device configured to absorb second light passing through both the color filter array and the first photoelectric conversion device and convert the absorbed second light into electrical signals. The first photoelectric conversion device includes a first photoelectric conversion layer configured to selectively absorb a mixed light of the first and second colors. The second photoelectric conversion device comprises a second photoelectric conversion layer configured to absorb light including a third color. Each of the first to third colors is one of three primary colors. The image sensor combines the electrical signals converted from the first and second photoelectric conversion devices to obtain electrical signals of the first to third colors.

Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.

Abstract: A semiconductor device includes a plurality of first slits disposed at a boundary region of contiguous memory blocks isolating the memory blocks from each other, and disposed to be spaced apart from each other by a predetermined distance in a first direction; at least one word line disposed between the first slits disposed in a square shape; at least one drain selection line disposed over the word line; and a plurality of isolation patterns disposed to isolate each segment of the at least one drain selection line into units of a block. The at least one word line is integrated into a single structure.

Abstract: A light emitting devices includes a first electrode, a hole transport region on the first electrode, a first emission layer on the hole transport region, the first emission layer to emit light of a first wavelength, a second emission layer on the hole transport region and to emit light of a second wavelength, an electron transport region on the first and second emission layers, and a second electrode on the electron transport region. The first emission layer includes a first sub-emission layer including a first hole transport host and a first sub-dopant to emit the light of the first wavelength, and a second sub-emission layer including a first electron transport and a second sub-dopant to emit the light of the first wavelength. The second emission layer includes a second hole transport host, a second electron transport host, and a second dopant to emit the light of the second wavelength.

Abstract: A micro-LED chip includes multiple micro-LEDs. At least one micro-LED of the multiple micro-LEDs includes: a first type conductive layer; a second type conductive layer stacked on the first type conductive layer; and a light emitting layer formed between the first type conductive layer and the second type conductive layer. The light emitting layer is continuously formed on the whole micro-LED chip, the multiple micro-LEDs sharing the light emitting layer. The micro-LED chip further includes: a top spacer formed on a top surface of the light emitting layer; a bottom spacer formed on a bottom surface of the light emitting layer; and an isolation structure formed between adjacent micro-LEDs.

Abstract: A fault isolation analysis method includes: providing a package structure in which there is an electrical fault; detecting whether the electrical fault is in interconnecting wires, and if the electrical fault is in the interconnecting wires, determining that the electrical fault is caused by the interconnecting wire; and if the electrical fault is not in the interconnecting wires, breaking the interconnecting wires to electrically isolate the chip structure from the substrate, then detecting whether the electrical fault is in the structure, and if the electrical fault is able to be detected, determining that the electrical fault is caused by the substrate, or if the electrical fault is not able to be detected, determining that the electrical fault is caused by the chip structure.

Abstract: A flexible display is disclosed. In one aspect, the display includes at least one first pattern including a plurality of display elements configured to display an image and extending in a first direction. The display device also includes at least one second pattern extending in a second direction and overlapping at least a portion of the first pattern. The second pattern has a curved shape in the first direction and the second direction crosses the first direction. The first and second patterns form at least one cavity region defining a space therebetween and the first and second patterns form a mesh structure.

Abstract: A semiconductor package includes: a base substrate; a semiconductor chip stack including a plurality of semiconductor chips stacked on the base substrate in a first direction and each having an upper surface on which a plurality of pads are disposed; and bonding wire structures electrically connecting the base substrate and the semiconductor chips. The semiconductor chip stack includes a lower semiconductor chip stack and an upper semiconductor chip stack on the lower semiconductor chip stack. The plurality of semiconductor chips include a first semiconductor chip at an uppermost portion of the lower semiconductor chip stack and second semiconductor chips. The plurality of pads include first pads, aligned in a second direction, and second pads, spaced apart from the first pads in a third direction. The first pad on the first semiconductor chip, has an area larger than an area of each of the first pads on the second semiconductor chips.

Abstract: A semiconductor package includes a substrate that includes a bonding pad, a first semiconductor chip disposed on the substrate, a second semiconductor chip disposed on a top surface of the first semiconductor chip that is opposite to the substrate, a chip pad disposed on the top surface of the first semiconductor chip, and a bonding wire that connects the chip pad to the bonding pad. The bonding wire includes a first upward protrusion and a second upward protrusion that are convexly curved in a direction away from the substrate. The second semiconductor chip has a first side surface between the first upward protrusion and the second upward protrusion.

Abstract: A memory device including a gain-cell memory cell capable of storing a large amount of data per unit area is provided. A peripheral circuit of the memory device is formed using a transistor formed on a semiconductor substrate, and a memory cell of the memory device is formed using a thin film transistor. A plurality of layers including thin film transistors where memory cells are formed are stacked above the semiconductor substrate, whereby the amount of data that can be stored per unit area can be increased. When an OS transistor with extremely low off-state current is used as the thin film transistor, the capacitance of a capacitor that accumulates charge can be reduced. In other words, the area of the memory cell can be reduced.

Abstract: An electronic component (10) for generating and emitting electromagnetic waves or single photons (48) comprises a layer system (12) of semiconductor materials. A middle layer (13) of gallium arsenide is arranged between a first layer (14) of aluminum gallium arsenide and a second layer (16) of aluminum gallium arsenide. A first outer layer (18) of gallium arsenide is provided on the first layer (14) of aluminum gallium arsenide; A second outer layer (20) of gallium arsenide is provided on the second layer (16) of aluminum gallium arsenide.

Abstract: According to one embodiment, a display device includes a substrate, a base layer, a plurality of light emitting elements, a resin layer, and a light reflecting layer. The resin layer is provided on the base layer, is filled in a gap between the light emitting elements, and has a flat surface. The light reflecting layer is provided above the flat surface, and includes a mirror surface and a plurality of openings.

Abstract: Provided herein is a cell of a magnetic random access memory (MRAM) circuit. The cell includes a horizontal outer perimeter and an access transistor including a first terminal, a second terminal, and a gate terminal. The cell includes a magnetic tunnel junction (MTJ) structure located in the horizontal outer perimeter and above the bottom electrode. The MTJ structure being centered within the horizontal outer perimeter. The cell includes a bottom electrode located entirely within the horizontal outer perimeter. The bottom electrode comprising a shape enabling the MTJ structure to be centered within the horizontal outer perimeter.

Abstract: A quantum dot composite includes a matrix and a plurality of quantum dots dispersed in the matrix, and a color conversion panel and a display panel including the same. The plurality of quantum dots include a metal including indium (In) and zinc and a non-metal including phosphorous (P), selenium, and sulfur, wherein the plurality of quantum dots includes a mole ratio of sulfur to indium of greater than or equal to about 3:1 and less than or equal to about 6:1, and a mole ratio of sulfur to selenium of greater than or equal about 0.69:1 and less than or equal to about 0.89, and a mole ratio of zinc to indium of greater than or equal to about 10:1 and less than or equal to about 12.4:1, and wherein the plurality of the quantum dots are configured to emit red light.

Abstract: A method of fabricating a metal gate transistor includes providing a substrate. Then, a high-k dielectric layer is formed to cover the substrate. Later, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. After the ion implantation process, a polysilicon gate is formed on the high-k dielectric layer. Next, an interlayer dielectric layer is formed to cover the substrate and the polysilicon gate. Finally, the polysilicon gate is replaced by a metal gate.

Abstract: The present disclosure provides a semiconductor device and a preparation method thereof. The semiconductor device comprises: a semiconductor substrate; a passivation layer, arranged on an upper surface of the semiconductor substrate; a protective layer, arranged on an upper surface of the passivation layer, a dummy opening being formed on the protective layer; and, a dummy bump, partially located in the dummy opening and closely attached to the protective layer.

Abstract: A semiconductor device assembly is provided. The assembly includes a redistribution layer (RDL) including a plurality of external contacts on a first side and a plurality of internal contacts on a second side opposite the first side. The assembly further includes a first die at least partially embedded in the RDL and having an active surface between the first side and the second side of the RDL. The assembly further includes one or more second dies disposed over the controller die and the RDL, wherein the one or more second dies electrically coupled to the internal contacts. The assembly further includes an encapsulant at least partially encapsulating the one or more second dies.

Abstract: Methods and semiconductor structures are provided. A method according to the present disclosure includes forming, over a substrate, a fin-shaped structure that includes a plurality of channel layers interleaved by a plurality of sacrificial layers, recessing a source/drain region of the fin-shaped structure to form a source/drain recess that extends into the substrate and exposes a portion of the substrate, selectively and partially recessing sidewalls of the plurality of sacrificial layers to form inner spacer recesses, forming inner spacers in the inner spacer recesses, selectively forming a buffer semiconductor layer on the exposed portion of the substrate, selectively depositing a first epitaxial layer on sidewalls of the plurality of channel layer and the buffer semiconductor layer such that a top surface of the buffer semiconductor layer is completely covered by the first epitaxial layer, and depositing a second epitaxial layer over the first epitaxial layer and the inner spacers.

Abstract: Provided is an array substrate, including: a first conductive wire, a second conductive wire and a first electrostatic protection unit, wherein the first electrostatic protection unit comprises a first thin-film transistor and a first capacitor; wherein a gate of the first thin-film transistor is suspended and is connected to a first electrode of the first thin-film transistor via the first capacitor, the first electrode of the thin-film transistor is connected to the first conductive wire, and a second electrode of the first thin-film transistor is connected to the second conductive wire.