Patents Examined by Yu-Hsi D Sun
  • Patent number: 11367667
    Abstract: A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: June 21, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Hong Wan Ng, Choon Kuan Lee, David J. Corisis, Chin Hui Chong
  • Patent number: 11366949
    Abstract: Embodiments of the present invention disclose an MRAM cell layout for 32 nm, 45 nm, and 65 nm CMOS process technology.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: June 21, 2022
    Assignee: III HOLDINGS 1, LLC
    Inventor: Krishnakumar Mani
  • Patent number: 11367670
    Abstract: An object is to improve the productivity of a power semiconductor device. A power semiconductor device according to the invention includes a circuit portion having a conductor for transmitting a current and a power semiconductor element, a first base portion and a second base portion facing each other with the circuit portion interposed therebetween, and a transfer mold member which is in contact with the conductor and the power semiconductor element and is filled in a space between the first base portion and the second base portion. The first base portion includes a first flat portion that is connected to a peripheral edge of the first base portion, and a first bent portion that connects the first flat portion and another portion of the first base portion and is plastically deformed. The transfer mold member is integrally configured in contact with the first flat portion.
    Type: Grant
    Filed: November 5, 2018
    Date of Patent: June 21, 2022
    Assignee: HITACHI ASTEMO, LTD.
    Inventor: Nobutake Tsuyuno
  • Patent number: 11362027
    Abstract: In one example, a semiconductor device includes a substrate with a top side, a bottom side, and a conductive structure. A first electronic component includes a first side, a second side, and first component terminals adjacent to the first side. The first component terminals face the substrate bottom side and are connected to the conductive structure. A second electronic component comprises a first side, a second side, and second component terminals adjacent to the second electronic component first side. The second electronic component second side is connected to the first electronic component second side so that the first component terminals and the second component terminals face opposite directions. Substrate interconnects are connected to the conductive structure, and a bottom encapsulant covers the substrate bottom side, the first electronic component, the second electronic component, and the substrate interconnects.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: June 14, 2022
    Assignee: Amkor Technology Singapore Holding Pte. Ltd.
    Inventors: Roger D. St. Amand, Louis W. Nicholls
  • Patent number: 11362043
    Abstract: A memory package includes a package substrate including power wiring and ground wiring. The memory package also includes a memory controller disposed over an upper surface of the package substrate and electrically connected to the power wiring and the ground wiring. The memory package further includes a memory chip disposed over the memory controller and electrically connected to the power wiring and the ground wiring. The memory package additionally includes a band pass filter disposed at one side of the memory controller over the upper surface of the package substrate and including an inductor and a capacitor which are connected in series. The inductor and the capacitor connected in series are electrically connected between the power wiring and the ground wiring.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: June 14, 2022
    Assignee: SK hynix Inc.
    Inventors: Byung Jun Bang, Sun Kyu Kong
  • Patent number: 11362071
    Abstract: Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with a first opening in an inner portion and a second opening in an outer portion of the substrate. Further, the semiconductor die assembly can include a master die attached to a front side of the substrate, where the master die includes a first bond pad proximate to the first opening and a second bond pad proximate to the second opening. The first and second bond pads of the master die can be coupled with first and second substrate bond pads on a back side of the substrate, opposite to the front side, using first and second bonding wires extending through the first and second openings, respectively.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: June 14, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Yeongbeom Ko, Youngik Kwon, Jong Sik Paek, Jungbae Lee
  • Patent number: 11355485
    Abstract: A semiconductor die is provided. The semiconductor die includes: at least one complementary metal oxide semiconductor (CMOS) circuit module electrically coupled to at least one memory die, the at least one memory die being separated from the semiconductor die; and a controller module electrically coupled to the CMOS circuit module and configured to control the at least one CMOS circuit module and the at least one memory die. A semiconductor package is also provided.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: June 7, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Yazhou Zhang, Chin-Tien Chiu, Shineng Ma
  • Patent number: 11342534
    Abstract: The present application relates to an encapsulation film, a method for producing the same, an organic electronic device comprising the same, and a method for preparing an organic electronic device using the same, which allows forming a structure capable of blocking moisture or oxygen introduced into an organic electronic device from the outside, and can prevent occurrence of bright spots of the organic electronic device.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: May 24, 2022
    Assignee: LG CHEM, LTD.
    Inventors: Jung Ok Moon, Hyun Jee Yoo, Yeong Bong Mok, Se Woo Yang
  • Patent number: 11342325
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) including a first fin structure and a second fin structure vertically extending from a semiconductor substrate, respectively. The first fin structure laterally extends along a first direction and has a first width. The second fin structure laterally extends along the first direction and has a second width that is less than the first width. A first plurality of nanostructures directly overlies the first fin structure and is vertically spaced from the first fin structure by a non-zero distance. A gate electrode continuously laterally extends along a second direction that is substantially perpendicular to the first direction. The gate electrode directly overlies the first and second fin structures, and wraps around the nanostructures.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: May 24, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chao Chou, Chih-Hao Wang, Shi Ning Ju, Kuo-Cheng Chiang, Wen-Ting Lan
  • Patent number: 11332661
    Abstract: A modified perovskite quantum dot material, a fabricating method thereof, and a display device are provided. Hydroxyl-modified perovskite quantum dots are obtained by adding an excess amount of hydroxyl-containing surface ligands to a solution of synthesized perovskite quantum dots. After high-speed centrifugation, the obtained perovskite quantum dots are redispersed into a non-polar alkyl solvent to form a solution. Further, an excess amount of ethyl orthosilicate is added to the solution, and after exposing the solution for a long period of time, the ethyl orthosilicate is hydrolyzed to form a triethoxysilane group. After centrifugation, modified perovskite quantum dots wrapped by the triethoxysilane groups are obtained, which effectively improves stability of the perovskite quantum dots.
    Type: Grant
    Filed: October 12, 2019
    Date of Patent: May 17, 2022
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Xu Chen
  • Patent number: 11335619
    Abstract: A semiconductor device, including: a heat sink which has a mounting surface, a heat radiation surface, a side surface and an engagement part, a semiconductor chip which is mounted on the mounting surface of the heat sink, a lead frame which is engaged with the engagement part of the heat sink, and a mold resin which seals the heat sink, the semiconductor chip and the lead frame, wherein the engagement part of the heat sink is disposed at a place which avoids the mounting surface of the heat sink. The engagement part of the heat sink is a dowel formed in the heat radiation surface of the heat sink. Further, the engagement part of the heat sink is a dowel formed in the side surface of the heat sink.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: May 17, 2022
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hiroaki Ichinohe
  • Patent number: 11329010
    Abstract: An anti-tamper layer is applied to a blank wafer. The layered wafer is then diced into shield dies. A shield die is oxide-to-oxide bonded to the top of an active die such that removing the shield die will damage the active die. The shield die may be sized and positioned such that wirebond pads along one or more edges of the active die remain exposed. The exposed wirebond pads may be used to electrically connect, via wirebonds, the active die to a substrate. A second shield die may be attached to the bottom of the active die to help protect against the use of bottom-to-top delayering.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: May 10, 2022
    Assignee: Cryptography Research, Inc.
    Inventors: Scott C. Best, Ming Li, Gary B. Bronner, Mark Evan Marson
  • Patent number: 11329027
    Abstract: A microelectronic package may be fabricated having a microelectronic die stack attached to a microelectronic substrate and at least one microelectronic device, which is separate from the microelectronic die stack, attached to the microelectronic substrate within the footprint of one of the microelectronic dice within the microelectronic die stack. In one embodiment, the microelectronic die stack may have a plurality of stacked microelectronic dice, wherein one microelectronic die of the plurality of microelectronic dice has a footprint greater than the other microelectronic die of the plurality of microelectronic dice, and wherein the at least one microelectronic device is attached to the one microelectronic die of the plurality of microelectronic dice having the greater footprint.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventor: Bilal Khalaf
  • Patent number: 11322602
    Abstract: Vertical field-effect transistor (VFET) devices and methods of forming VFET devices are provided. The methods may include forming a preliminary VFET on a substrate. The preliminary VFET may include a bottom source/drain region on the substrate, a channel region on the bottom source/drain region, a top source/drain region on the channel region, a patterned sacrificial layer on a side surface of the channel region, and an insulating layer. The top source/drain region and the patterned sacrificial layer may be enclosed by the insulating layer. The methods may also include forming a contact opening extending through the insulating layer and exposing a portion of the patterned sacrificial layer, forming a cavity between the channel region and the insulating layer by removing the patterned sacrificial layer through the contact opening, and forming a gate electrode in the cavity.
    Type: Grant
    Filed: February 19, 2020
    Date of Patent: May 3, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hwi Chan Jun, Kang-Ill Seo, Jeong Hyuk Yim
  • Patent number: 11315948
    Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: April 26, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sang-Yong Park, Jintaek Park
  • Patent number: 11309236
    Abstract: A semiconductor device includes a pair of spacers disposed on the surface of a substrate, the spacers are a first height and spaced from each other at a first distance along a first direction. A first semiconductor chip is mounted on the substrate surface. The first semiconductor chip has a second height that is less than the first height. The first semiconductor chip can be connected to the substrate with bonding wires or the like. A second semiconductor chip is mounted on the spacers and spans the distance between the spacers. The second semiconductor chip is above at least a portion of the first semiconductor chip. A projecting section is provided on the surface of the substrate between the spacers in the first direction. The projecting section is between the first semiconductor chip and an outer edge of the substrate and protrudes upward from the surface of the substrate.
    Type: Grant
    Filed: February 28, 2020
    Date of Patent: April 19, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Minoru Kurata
  • Patent number: 11302665
    Abstract: The power semiconductor apparatus includes: a semiconductor device 401; a bonding layer on chip 416 disposed on an upper surface of the semiconductor device; and a metal lead 419 disposed on the upper surface of the semiconductor device and bonded to the bonding layer on chip, wherein the metal lead 420 has a three-laminated structure including: a second metal layer 420b having a CTE equal to or less than 5×10?6/° C., for example; and a first metal layer 420a and a third metal layer 420c sandwiching the second metal layer and having a CTE equal to or greater than the CTE of the second metal layer. Provided is a power semiconductor apparatus capable of improving reliability thereof by reducing a thermal stress to a bonding layer between a semiconductor power device and a metal lead positioned on an upper surface thereof, and reducing a resistance of the metal lead.
    Type: Grant
    Filed: November 6, 2019
    Date of Patent: April 12, 2022
    Assignee: ROHM CO., LTD.
    Inventors: Takukazu Otsuka, Seita Iwahashi, Maiko Hatano, Ryuta Watanabe, Katsuhiko Yoshihara
  • Patent number: 11302615
    Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.
    Type: Grant
    Filed: April 5, 2020
    Date of Patent: April 12, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anindya Poddar, Woochan Kim, Vivek Kishorechand Arora
  • Patent number: 11302664
    Abstract: A method of manufacturing a die package structure includes steps described below. A conductive substrate with a plurality of trenches is provided. A die is disposed in each of the trenches. A conductive layer is formed covering the dies and the conductive substrate. A patterned photoresist layer with a plurality of openings is formed exposing a plurality of areas of the conductive layer. A mask is formed on each of the areas of the conductive layer. The patterned photoresist layer is removed after forming the masks. By using the masks, the conductive layer and the conductive substrate under thereof are selectively etched to a predetermined depth to form a plurality of conductive bumps and a plurality of electrodes, in which a remaining of the conductive substrate includes a bottom substrate, the electrodes and the conductive bumps. An upper sealing layer is formed covering the bottom substrate and the dies.
    Type: Grant
    Filed: May 31, 2020
    Date of Patent: April 12, 2022
    Assignee: Comchip Technology Co., Ltd.
    Inventors: Chien-Chih Lai, Hung-Wen Lin
  • Patent number: 11296002
    Abstract: A semiconductor device package includes a substrate, a first electronic component and a first encapsulant. The substrate has a first surface and a second surface opposite to the first surface. The first electronic component is disposed on the first surface of the substrate. The first encapsulant is disposed on the first surface of the substrate and covers the first electronic component. The first encapsulant has a first surface facing away the first surface of the substrate and includes a recess at an edge of the first surface of the first encapsulant.
    Type: Grant
    Filed: January 3, 2020
    Date of Patent: April 5, 2022
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu