Patents Examined by Yu-Hsi D Sun
  • Patent number: 11943922
    Abstract: A non-volatile memory includes a plurality of word lines connected to non-volatile memory cells, a plurality of driver lines configured to carry one or more word line voltages, and a plurality of word line switches that selectively connect the driver lines to the word lines. To more efficiently utilize space on the die, the word line switches are arranged in a plurality of three dimensional stacks such that each stack of the plurality of stacks comprises multiple word line switches vertically stacked.
    Type: Grant
    Filed: November 11, 2023
    Date of Patent: March 26, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Guangyuan Li, Qinghua Zhao, Sudarshan Narayanan, Yuji Totoki, Fumiaki Toyama
  • Patent number: 11942402
    Abstract: An isolator device includes a laminate die having a dielectric laminate material with a metal laminate layer on one side of the dielectric laminate material, the metal laminate layer being a patterned layer providing at least a first plate, including a dielectric layer over the first plate that includes an aperture exposing a portion of the first plate. An integrated circuit (IC) including a substrate having a semiconductor surface includes circuitry including a transmitter and/or a receiver, the IC including a top metal layer providing at least a second plate coupled to a node in the circuitry, with at least one passivation layer on the top metal layer. A non-conductive die attach (NCDA) material for attaching a side of the dielectric laminate material is opposite the metal laminate layer to the IC so that the first plate is at least partially over the second plate to provide a capacitor.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: March 26, 2024
    Assignee: Texas Instruments Incorporated
    Inventor: Thomas Dyer Bonifield
  • Patent number: 11942392
    Abstract: An IC device includes first and second resistors. The first resistor includes first and second metal segments extending in a first direction in a first metal layer, and a third metal segment extending in a second direction in a second metal layer, and electrically connecting the first and second metal segments. The second resistor includes fourth and fifth metal segments extending in the first direction in the first metal layer, and a sixth metal segment extending in the second direction in a third metal layer, and electrically connecting the fourth and fifth metal segments. The fourth and fifth metal segment have a width greater than a width of the first and second metal segments, the fourth metal segment is between the first and second metal segments and separated from the first metal segment by a distance, and a fourth and fifth metal segment separation is greater than the distance.
    Type: Grant
    Filed: January 24, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jaw-Juinn Horng, Szu-Lin Liu, Wei-Lin Lai
  • Patent number: 11935876
    Abstract: A light-emitting element ink, a display device, and a method of fabricating the display device are provided. The light-emitting element ink includes a light-emitting element solvent, light-emitting elements dispersed in the light-emitting element solvent, each of the light-emitting elements including a plurality of semiconductor layers and an insulating film that surrounds parts of outer surfaces of the semiconductor layers, and a surfactant dispersed in the light-emitting element solvent, the surfactant including a fluorine-based and/or a silicon-based surfactant.
    Type: Grant
    Filed: April 27, 2021
    Date of Patent: March 19, 2024
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jun Bo Sim, Duk Ki Kim, Yong Hwi Kim, Hyo Jin Ko, Chang Hee Lee, Chan Woo Joo, Jae Kook Ha, Na Mi Hong
  • Patent number: 11929382
    Abstract: Photosensitive devices and associated methods are provided. In one aspect, for example, a photosensitive imager device can include a semiconductor layer having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor layer and positioned to interact with electromagnetic radiation. The textured region can be formed from a series of shallow trench isolation features.
    Type: Grant
    Filed: July 7, 2021
    Date of Patent: March 12, 2024
    Assignee: SIONYX, INC.
    Inventors: Homayoon Haddad, Jutao Jiang
  • Patent number: 11929343
    Abstract: There is provided a novel Cu bonding wire that achieves a favorable FAB shape and achieve a favorable bond reliability of the 2nd bonding part even in a rigorous high-temperature environment. The bonding wire for semiconductor devices includes a core material of Cu or Cu alloy, and a coating layer having a total concentration of Pd and Ni of 90 atomic % or more formed on a surface of the core material. The bonding wire is characterized in that: in a concentration profile in a depth direction of the wire obtained by performing measurement using Auger electron spectroscopy (AES) so that the number of measurement points in the depth direction is 50 or more for the coating layer, a thickness of the coating layer is 10 nm or more and 130 nm or less, an average value X is 0.2 or more and 35.
    Type: Grant
    Filed: March 16, 2022
    Date of Patent: March 12, 2024
    Assignee: NIPPON MICROMETAL CORPORATION
    Inventors: Daizo Oda, Motoki Eto, Takashi Yamada, Teruo Haibara, Ryo Oishi
  • Patent number: 11923258
    Abstract: An example includes: a substrate having a first package surface, having a second package surface opposite the first package surface, and having a die cavity with a depth extending into the first package surface; a semiconductor die having bond pads on a first die surface and having a second die surface opposite the first die surface, the semiconductor die having a die thickness, the second die surface of the semiconductor die mounted in the die cavity; a cover over a portion of the first die surface; conductors coupling the bond pads of the semiconductor die to bond fingers on the first package surface of the substrate; and dielectric material over the conductors, the bond fingers, the bond pads, at least a portion of the first semiconductor die and at least a portion of the cover, wherein the dielectric material extends above the first package surface of the substrate.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: March 5, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: William Robert Morrison, Bradley Morgan Haskett
  • Patent number: 11923263
    Abstract: A semiconductor device includes a substrate, a chip underlying the substrate, a chip overlying the substrate, and a dummy die overlying the substrate. A pattern of the dummy die includes a first interior sidewall and a second interior sidewall, and a stress relief material between the first interior sidewall and the second interior sidewall to form a dummy die stress balance pattern.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventor: Jen-Yuan Chang
  • Patent number: 11925023
    Abstract: A three-dimensional semiconductor device includes a stacked structure including a plurality of conductive layers stacked on a substrate, a distance along a first direction between sidewalls of an upper conductive layer and a lower conductive layer being smaller than a distance along a second direction between sidewalls of the upper conductive layer and the lower conductive layer, the first and second directions crossing each other and defining a plane parallel to a surface supporting the substrate, and vertical channel structures penetrating the stacked structure.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: March 5, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Yong Park, Jintaek Park
  • Patent number: 11923281
    Abstract: A semiconductor package includes a metallic pad and leads, a semiconductor die attached to the metallic pad, the semiconductor die including an active side with bond pads opposite the metallic pad, a wire bond extending from a respective bond pad of the semiconductor die to a respective lead of the leads, a heat spreader over the active side of the semiconductor die with a gap separating the active side of the semiconductor die from the heat spreader, an electrically insulating material within the gap and in contact with the active side of the semiconductor die and the heat spreader; and mold compound covering the semiconductor die and the wire bond, and partially covering the metallic pad and the heat spreader, with the metallic pad exposed on a first outer surface of the semiconductor package and with the heat spreader exposed on a second outer surface of the semiconductor package.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: March 5, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anindya Poddar, Woochan Kim, Vivek Kishorechand Arora
  • Patent number: 11917820
    Abstract: A method for fabricating semiconductor device includes forming an alternating stack that includes a lower multi-layered stack and an upper multi-layered stack by alternately stacking a dielectric layer and a sacrificial layer over a substrate, forming a vertical trench that divides the upper multi-layered stack into dummy stacks, and forming an asymmetric stepped trench that is extended downward from the vertical trench to divide the lower multi-layered stack into a pad stack and a dummy pad stack, wherein forming the asymmetric stepped trench includes forming a first stepped sidewall that is defined at an edge of the pad stack, and forming a second stepped sidewall that is defined at an edge of the dummy pad stack and occupies less area than the first stepped sidewall.
    Type: Grant
    Filed: July 6, 2021
    Date of Patent: February 27, 2024
    Assignee: SK hynix Inc.
    Inventors: Eun-Ho Kim, Eun-Joo Jung, Jong-Hyun Yoo, Ki-Jun Yun, Sung-Hoon Lee
  • Patent number: 11908824
    Abstract: The present invention relates to a semiconductor package in which a metal bridge, which is bent and has elasticity and a non-vertical structure, may protect a semiconductor chip in such a way that push-stress occurring while molding is relieved by being absorbed or dispersed by being diverted, a method of manufacturing the same, and the metal bridge applied to the semiconductor package.
    Type: Grant
    Filed: January 3, 2022
    Date of Patent: February 20, 2024
    Assignee: JMJ Korea Co., Ltd.
    Inventor: Yun Hwa Choi
  • Patent number: 11908837
    Abstract: In a semiconductor device, a first interposer has a first main surface. A second interposer is disposed on the first main surface. The second interposer has a second main surface on a side opposite to the first interposer. A material of the second interposer is different from that of the first interposer. A first semiconductor chip has a first front surface. The first semiconductor chip is mounted on the second main surface through a plurality of bump electrodes with the first front surface facing the second main surface. The first semiconductor chip includes a volatile memory circuit. A second semiconductor chip is mounted on a plurality of electrode patterns disposed on the first main surface or the second main surface through a plurality of bonding wires. The second interposer overlaps the first semiconductor chip in a direction perpendicular to the first main surface.
    Type: Grant
    Filed: August 23, 2021
    Date of Patent: February 20, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Soichiro Ibaraki
  • Patent number: 11908968
    Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated in a transparent block. An opaque conductive layer is applied to a top surface and a side surface of the transparent block. The receiver is mounted to the opaque conductive layer at the top surface. An electrical connection is made between the receiver and the opaque conductive layer. A conductive strip is also mounted to the side surface of the transparent block and isolated from the opaque conductive layer. A further electrical connection is made between the receiver and the conductive strip.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: February 20, 2024
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Remi Brechignac, Jean-Michel Riviere
  • Patent number: 11901337
    Abstract: A semiconductor device includes a first wiring substrate having a first surface and a second surface opposite to the first surface, and including a plurality of first electrode pads on the first surface, and a second wiring substrate having a third surface facing the first surface and a fourth surface opposite to the third surface, and including a plurality of second electrode pads on the third surface. A plurality of first semiconductor chips are stacked between the first surface and the third surface. A first columnar electrode extends in an oblique direction with respect to a first direction substantially perpendicular to the first surface and the third surface, and connects between the plurality of first electrode pads and the plurality of second electrode pads. A first resin layer covers the plurality of first semiconductor chips and the first columnar electrode between the first surface and the third surface.
    Type: Grant
    Filed: September 2, 2021
    Date of Patent: February 13, 2024
    Assignee: KIOXIA CORPORATION
    Inventor: Yasuo Otsuka
  • Patent number: 11901421
    Abstract: A semiconductor device may include a substrate, an interface insulation pattern, a gate insulation pattern, a threshold voltage controlling metal pattern and a conductive pattern. The interface insulation pattern may be formed on the substrate. The gate insulation pattern including an oxide having a dielectric constant higher than that of silicon oxide may be formed on the interface insulation pattern. The threshold voltage controlling metal pattern may be formed on the gate insulation pattern. The conductive pattern may be formed on the threshold voltage controlling metal pattern. First dopants including at least fluorine may be included within and at at least one surface of the gate insulation pattern and at an upper surface of an interface insulation pattern contacting the gate insulation pattern. The semiconductor device may have excellent electrical characteristics.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: February 13, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hokyun An, Bumsoo Kim, Hyunseung Kim, Guangfan Jiao
  • Patent number: 11894344
    Abstract: An apparatus comprising: a die stack comprising at least one die pair, the at least one die pair having a first die over a second die, the first die and the second die both having a first surface and a second surface, the second surface of the first die over the first surface of the second die; and an adhesive film between the first die and the second die of the at least one die pair; wherein the adhesive film comprises an insulating layer and a conductive layer, the insulating layer adhering to the second surface of the first die and the conductive layer adhering to the first surface of the second die.
    Type: Grant
    Filed: April 6, 2022
    Date of Patent: February 6, 2024
    Assignee: Intel Corporation
    Inventors: Zhijun Xu, Bin Liu, Yong She, Zhicheng Ding
  • Patent number: 11894334
    Abstract: Embodiments disclosed herein include wire bonds and tools for forming wire bonds. In an embodiment, a wire bond may comprise a first attachment ball, and a first wire having a first portion contacting the first attachment ball and a second portion. In an embodiment, the wire bond may further comprise a second attachment ball, and a second wire having a first portion contacting the second attachment ball and a second portion. In an embodiment, the second portion of the first wire is connected to the second portion of the second wire.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: February 6, 2024
    Assignee: Intel Corporation
    Inventors: Yuhong Cai, Bilal Khalaf, Yi Xu
  • Patent number: 11887920
    Abstract: Embodiments of a redistribution layer structure comprise a low-k dielectric material and incorporating a reinforcement structure proximate and inward of a peripheral edge thereof, the reinforcement structure comprising conductive material electrically isolated from conductive paths through the RDL structure. Semiconductor packages including an embodiment of the RDL structure and methods of fabricating such RDL structures are also disclosed.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: January 30, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Hyunsuk Chun, Chan H. Yoo, Tracy N. Tennant
  • Patent number: 11881441
    Abstract: Stacked die semiconductor packages may include a spacer die disposed between stacked dies in the semiconductor package and the semiconductor package substrate. The spacer die translates thermally induced stresses on the solder connections between the substrate and an underlying member, such as a printed circuit board, from electrical structures communicably or conductively coupling the semiconductor package substrate to the underlying structure to mechanical structures that physically couple the semiconductor package to the underlying structure. The footprint area of the spacer die is greater than the sum of the footprint areas of the individual stacked dies in the semiconductor package and less than or equal to the footprint area of the semiconductor package substrate. The spacer die may have nay physical configuration, thickness, shape, or geometry. The spacer die may have a coefficient of thermal expansion similar to that of the lowermost semiconductor die in the die stack.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: January 23, 2024
    Assignee: Intel Corporation
    Inventors: Sireesha Gogineni, Andrew Kim, Yong She, Karissa J. Blue