Abstract: A vertical-wire package-in-package includes at least two memory-die stacks that form respective memory modules that are stacked vertically on a bond-wire board. Each memory die in the memory-die stack includes a vertical bond wire that emerges from a matrix for connection. The matrix encloses the memory-die stack, the spacer, and a redistribution layer. At least two memory modules are assembled in a vertical-wire package-in-package.

Abstract: A semiconductor package according to one embodiment comprises a substrate. A semiconductor chip is provided on the substrate. A resin layer is configured to cover the semiconductor chip on the substrate. A metal film is configured to cover a surface and side surfaces of the resin layer. The metal film is a laminated film including first to fourth metal layers. The first metal layer is configured to cover the resin layer. The second metal layer includes a first metal material that is different from a material of the first metal layer. The third metal layer includes an alloy of the first metal material forming the second metal layer and a second metal material different from the first metal material. The fourth metal layer is configured to cover the second or third metal layer.

Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate; a gate structure disposed over the substrate and over a channel region of the semiconductor device, wherein the gate structure includes a gate stack and spacers disposed along sidewalls of the gate stack, the gate stack including a gate dielectric layer and a gate electrode; a first metal layer disposed over the gate stack, wherein the first metal layer laterally contacts the spacers over the gate dielectric layer and the gate electrode; and a gate via disposed over the first metal layer.

Abstract: An active matrix display where in one embodiment each cell comprises: a driving circuit for providing current to light emitting devices placed in the cell under the control of a data driver signal, a first light emitting device location connected to the driving circuit and a second light emitting device location connected in series to the first light emitting device location. A first thin-film transistor (TFT) is connected in parallel with the first light emitting device location and a second TFT is connected in parallel with the second light emitting device location, its gate node connected to the gate node of the first TFT. One terminal of a third TFT is connected to the gate nodes of the first and second TFTs and selectively connects a control signal to the first and second TFTs under the control of a scan driver signal. The control signal determines which of a first or second light emitting device placed in the cell emits light when the driving circuit provides current.

Abstract: There is provided a novel Cu bonding wire that achieves a favorable FAB shape and reduces a galvanic corrosion in a high-temperature environment to achieve a favorable bond reliability of the 2nd bonding part. The bonding wire for semiconductor devices includes a core material of Cu or Cu alloy, and a coating layer having a total concentration of Pd and Ni of 90 atomic % or more formed on a surface of the core material. The bonding wire is characterized in that: in a concentration profile in a depth direction of the wire obtained by performing measurement using Auger electron spectroscopy (AES) so that the number of measurement points in the depth direction is 50 or more for the coating layer, a thickness of the coating layer is 10 nm or more and 130 nm or less, an average value X is 0.2 or more and 35.

Abstract: A packaging method includes providing a substrate structure, including a core substrate, a plurality of first conductive pads at a first surface of the core substrate, and a plurality of packaging pads at a second surface of the core substrate; and packaging a plurality of semiconductor chips onto the substrate structure at the second surface of the core substrate, including forming a first metal wire to connect with a chip-contact pad of a semiconductor chip, and forming a molding compound on the second surface of the core substrate to encapsulate the plurality of semiconductor chips. One end of the first metal wire connects to the chip-contact pad, and another end of the first metal wire is exposed at the surface of the molding compound. The packaging method further includes forming a first metal pad on the surface of the molding compound to electrically connect with the first metal wire.

Abstract: A flexible display is disclosed. In one aspect, the display includes at least one first pattern including a plurality of display elements configured to display an image and extending in a first direction. The display device also includes at least one second pattern extending in a second direction and overlapping at least a portion of the first pattern. The second pattern has a curved shape in the first direction and the second direction crosses the first direction. The first and second patterns form at least one cavity region defining a space therebetween and the first and second patterns form a mesh structure.

Abstract: A semiconductor device includes a rigid flex circuit that has a first rigid region and a second rigid region that are electrically connected by a flexible portion. A first die is mounted to a first side of the first rigid region. A second die is mounted to a second side of the second rigid region. The first and second sides are on opposite sides of the rigid flex circuit. The flexible portion is bent to hold the first and second rigid regions in generally vertical alignment with each other.

Abstract: A semiconductor device that is suitable for miniaturization and higher density is provided. A semiconductor device includes a first transistor over a semiconductor substrate, a second transistor including an oxide semiconductor over the first transistor, and a capacitor over the second transistor. The capacitor includes a first conductor, a second conductor, and an insulator. The second conductor covers a side surface of the first conductor with an insulator provided therebetween.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack is formed comprising vertically-alternating first tiers and second tiers above the conductor tier. The stack comprises laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from that of the second tiers. A lowest of the first tiers is thicker than the first tiers there-above. The first-tier material is isotropically etched selectively relative to the second-tier material to form void-space in the first tiers. Conducting material is deposited into the trenches and into the void-space in the first tiers. The conducting material fills the void-space in the first tiers that are above the lowest first tier.

Abstract: A display device includes: a substrate comprising a display area and a peripheral area outside the display area; a first connection line in the display area, the first connection line comprising a first portion extending along a first column of the display area and in the first column, a third portion extending along a second column of the display area and in the second column, and a second portion connecting the first portion to the third portion; and a second connection line in the peripheral area and connected to the third portion of the first connection line and a data line in a third column of the display area.

Abstract: A method for producing a hybrid structure, the hybrid structure including at least one structured Majorana material and at least one structured superconductive material arranged thereon includes producing, on a substrate, a first mask for structured application of the Majorana material and a further mask for structured growth of the at least one superconductive material, which are aligned relatively to one another, and applying the at least one structured superconductive material to the structured Majorana material with the aid of the further mask. The structured application of the Majorana material and of the at least one superconductive material takes place without interruption in an inert atmosphere.

Abstract: A vacuum channel transistor having a vertical gate-all-around (GAA) architecture provides high performance for high-frequency applications, and features a small footprint compared with existing planar devices. The GAA vacuum channel transistor features stacked, tapered source and drain regions that are formed by notching a doped silicon pillar using a lateral oxidation process. A temporary support structure is provided for the pillar during formation of the vacuum channel. Performance of the GAA vacuum channel transistor can be tuned by replacing air in the channel with other gases such as helium, neon, or argon. A threshold voltage of the GAA vacuum channel transistor can be adjusted by altering dopant concentrations of the silicon pillar from which the source and drain regions are formed.

Abstract: A method of manufacturing an MRAM device, the method including forming a first magnetic layer on a substrate; forming a first tunnel barrier layer on the first magnetic layer such that the first tunnel barrier layer includes a first metal oxide, the first metal oxide being formed by oxidizing a first metal layer at a first temperature; forming a second tunnel barrier layer on the first tunnel barrier layer such that the second tunnel barrier layer includes a second metal oxide, the second metal oxide being formed by oxidizing a second metal layer at a second temperature that is greater than the first temperature; and forming a second magnetic layer on the second tunnel barrier layer.

Abstract: The present disclosure provides a semiconductor package structure and a method of manufacturing the same. The semiconductor package structure includes a substrate, a first electronic component, an interlayer, a third electronic component and an encapsulant. The first electronic component is disposed on the substrate. The first electronic component has an upper surface and a lateral surface and a first edge between the upper surface and the lateral surface. The interlayer is on the upper surface of the first electronic component. The third electronic component is attached to the upper surface of the first electronic component via the interlayer. The encapsulant encapsulates the first electronic component and the interlayer. The interlayer does not contact the lateral surface of the first electronic component.

Abstract: Metallization structures under a semiconductor device layer. A metallization structure in alignment with semiconductor fin may be on a side of the fin opposite a gate stack. Backside and/or frontside substrate processing techniques may be employed to form such metallization structures on a bottom of a semiconductor fin or between bottom portions of two adjacent fins. Such metallization structures may accompany interconnect metallization layers that are over a gate stack, for example to increase metallization layer density for a given number of semiconductor device layers.

Abstract: A method of fabricating a metal gate transistor includes providing a substrate. An interlayer dielectric layer covers the substrate. A dummy gate is embedded in the interlayer dielectric layer. A high-k dielectric layer is disposed between the dummy gate and the substrate. Later, the dummy gate is removed to form a trench, and the high-k dielectric layer is exposed through the trench. After the dummy gate is removed, an ion implantation process is performed to implant fluoride ions into the high-k dielectric layer. Finally, after the ion implantation process, a metal gate is formed to fill in the trench.

Abstract: An organic light emitting diode display device, including a flexible substrate; pixels on the flexible substrate, the pixels including an organic emission layer; a pixel definition layer between the pixels, the pixel definition layer including openings; an encapsulation layer covering the pixels; and a conductive light shielding member on the encapsulation layer, the conductive light shielding member not overlapped with the pixels, and overlapped with the pixel definition layer.

Abstract: It is disclosed to obtain a frequency transformed radiomap data set by applying a discrete frequency transform to an original radiomap data set. It is also disclosed to obtain a reconstructed radiomap data set by applying an inverse discrete frequency transform to a frequency transformed radiomap data set.