Abstract: A semiconductor package includes a package substrate which includes a substrate base and a plurality of wiring patterns, a lower semiconductor chip, and an upper semiconductor chip. The substrate base includes a chip-accommodating cavity and the plurality of wiring patterns include a plurality of bottom wiring patterns on a bottom surface of the substrate base and a plurality of top wiring patterns on a top surface of the substrate base. The lower semiconductor chip is disposed in the chip-accommodating cavity and is connected to the plurality of bottom wiring patterns through a plurality of lower bonding wires. The upper semiconductor chip includes a first portion which is attached to the lower semiconductor chip and a second portion which overhangs the lower semiconductor chip.

Abstract: Apparatuses and methods for coupling semiconductor devices are disclosed. In a group of semiconductor devices (e.g., a stack of semiconductor devices), a signal is provided to a point of coupling at an intermediate semiconductor device of the group, and the signal is propagated away from the point of coupling over different (e.g., opposite) signal paths to other semiconductor devices of the group. Loading from the point of coupling at the intermediate semiconductor device to other semiconductor devices of a group may be more balanced than, for example, having a point of coupling at semiconductor device at an end of the group (e.g., a lowest semiconductor device of a stack, a highest semiconductor device of the stack, etc.) and providing a signal therefrom. The more balanced topology may reduce a timing difference between when signals arrive at each of the semiconductor devices.

Abstract: A display substrate includes a display region and hollowed-out grooves provided at a periphery of the display region. The display substrate includes a first organic base layer, a light-emitting unit provided on the base structure layer and located at the display region; the first organic base layer is provided with a groove structure located between the hollowed-out grooves and the display region. The display substrate further includes a first inorganic package layer for covering the light-emitting unit and the groove structure.

Abstract: Semiconductor devices may include a first semiconductor chip, a first redistribution layer on a bottom surface of the first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a second redistribution layer on a bottom surface of the second semiconductor chip, a mold layer extending on sidewalls of the first and second semiconductor chips and on the bottom surface of the first semiconductor chip, and an external terminal extending through the mold layer and electrically connected to the first redistribution layer. The second redistribution layer may include an exposed portion. The first redistribution layer may include a first conductive pattern electrically connected to the first semiconductor chip and a second conductive pattern electrically insulated from the first semiconductor chip. The exposed portion of the second redistribution layer and the second conductive pattern of the first redistribution layer may be electrically connected by a first connection wire.

Abstract: The disclosed technology generally relates to a barrier layer comprising titanium silicon nitride, and more particularly to a barrier layer for nonvolatile memory devices, and methods of forming the same. In one aspect, a method of forming an electrode for a phase change memory device comprises forming over a semiconductor substrate an electrode comprising titanium silicon nitride (TiSiN) on a phase change storage element configured to store a memory state. Forming the electrode comprises exposing a semiconductor substrate to one or more cyclical vapor deposition cycles, wherein a plurality of the cyclical vapor deposition cycles comprises an exposure to a Ti precursor, an exposure to a N precursor and an exposure to a Si precursor.

Abstract: In an example embodiment, a method comprises: forming first spacers adjacent to a memory cell formed on a substrate, each of the first spacers being formed in direct contact with the substrate, where forming the memory cell includes forming a control gate electrode and a tunnel oxide layer over the substrate and subsequently etching completely at least the control gate electrode and the tunnel oxide layer that are disposed beyond the memory cell; forming an interlayer dielectric layer over the memory cell and the first spacers; forming a contact hole through the interlayer dielectric layer to at least reach the substrate; subsequent to forming the contact hole, forming a second spacer adjacent to one of the first spacers, where a height of the second spacer is greater than a height of the first spacers, the second spacer substantially contacting the substrate and the interlayer dielectric layer; and forming a contact in the contact hole.

Abstract: A semiconductor package includes a base substrate, an insulating layer including a first region disposed on the base substrate and in which first and second openings are disposed and a second region, a remaining region of the base substrate other than the first region, a first semiconductor chip disposed on the base substrate and including bonding pads disposed closely to a first edge, at least one second semiconductor chip stacked on the first semiconductor chip in the form of a staircase toward a second edge, parallel to the first edge, and a molding portion covering the base substrate to encapsulate the first and second semiconductor chips, wherein the length of the first edge is disposed to overlap the second region, both ends of the second edge are disposed to overlap the first and second openings, and the molding portion fills the first and second openings.

Abstract: A semiconductor device includes a printed circuit board having a plurality of first electrode pads on a first main surface and a plurality of second electrode pads electrically connected to at least one of the plurality of first electrode pads on a second main surface, a first chip disposed on the first main surface and having a non-volatile memory; a second chip having a third electrode pad and a control circuit configured to control an operation of the non-volatile memory, a dummy chip having a component that has a higher thermal conductivity than a substrate of the second chip, and a sealing member sealing the first, second, and dummy chips. The third electrode pad is connected to the component of the dummy chip via a first wiring, and the component of the dummy chip is connected to one of the plurality of first electrode pads via a second wiring.

Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.

Abstract: A fan-out semiconductor package includes connection pads of a semiconductor chip that are redistributed and electrically connected to connection terminals by an interconnection member. In the fan-out semiconductor package, disposition forms of vias and pads in the interconnection member are designed so that stress may be reduced, such that reliability is improved.

Abstract: A semiconductor package includes; a chip structure including vertically stacked semiconductor chips disposed on a package substrate, a spacer disposed on an uppermost semiconductor chip among the semiconductor chips, an encapsulant covering at least part of the chip structure, and including an upper portion of the encapsulant covering at least part of the spacer, and a marking pattern visually identifiable through an opening in the upper portion of the encapsulant selectively exposing portions of the spacer.

Abstract: A packaged integrated circuit device includes a substrate having a surface thereon. A spacer and a first semiconductor chip are provided at spaced-apart locations on a first portion of the surface of the substrate. This first portion of the surface of the substrate has a lateral area equivalent to a sum of: (i) a lateral footprint of the spacer, (ii) a lateral footprint of the first semiconductor chip, and (iii) an area of an entire lateral space between the spacer and the first semiconductor chip. A stack of second semiconductor chips is provided, which extends on the spacer and on the first semiconductor chip.

Abstract: The disclosure has an object to achieve a high level of height precision for spacers on a back plane. A display device includes: edge covers having a plurality of openings in which first electrodes are exposed; and a planarization film having first flat portions, second flat portions, and contact holes. The plurality of openings respectively overlap the first flat portions in a plan view. The second flat portions are located between the plurality of openings in a plan view. Each edge cover overlapping one of the first flat portions in a plan view has, on a second electrode side, a surface that has a first height from a bottom surface of the planarization film on a substrate side. Each second flat portion has, on the second electrode side, a surface that has a second height from the bottom surface. The first height is smaller than the second height.

Abstract: Provided is a method for bonding an insulated coating wire, which is capable of stably bonding a metal wire in an insulated coating wire and an electrode. One aspect of the present invention provides a method for bonding an insulated coating wire for electrically connecting a first electrode 12 and a second electrode to each other by an insulated coating wire 11 in which a metal wire is coated with an organic substance, the method including: a step (a) for placing the insulated coating wire 11 onto the first electrode 12; a step (b) for exposing a metal wire from the insulated coating wire; and a step (c) for forming a first bump over the exposed metal wire and the first electrode to electrically connect the metal wire to the first electrode.

Abstract: Disclosed is a semiconductor package comprising a first semiconductor chip on a substrate, a second semiconductor chip between the substrate and the first semiconductor chip, and a spacer between the substrate and the first semiconductor chip. The substrate includes a first substrate pad between the second semiconductor chip and the spacer. The second semiconductor chip includes a chip pad and a signal wire. The spacer includes a first dummy pad on the spacer and a first dummy wire coupled to the first dummy pad. The first dummy pad is adjacent to the second semiconductor chip. The first semiconductor chip is attached to the second semiconductor chip and the spacer by an adhesive layer on the first semiconductor chip. A portion of each of the signal wire and the first dummy wire are in the adhesive layer.

Abstract: The present disclosure relates to a display device and a method of manufacturing the same. The display device includes: a plurality of display units, each display unit including one or more pixels; and a plurality of elastically stretchable stretching units respectively connected among the plurality of display units and forming elastic connection points with the display units, the stretching units and the plurality of display units forming a net-shaped distribution structure, wherein in a state that the display device is not under tension, a connection lines between the elastic connection points at both ends of the stretching unit are not parallel to a normal of the display units connected with at least one end of the stretching unit at the elastic connection points.

Abstract: Embodiments disclosed herein include an electronics package and methods of forming such electronics packages. In an embodiment, the electronics package comprises a package substrate, and a first die coupled to the package substrate. In an embodiment, a cavity is formed through the package substrate. In an embodiment, the cavity is within a footprint of the first die. In an embodiment, the electronics package further comprises a thermal stack in the cavity. In an embodiment, the thermal stack contacts the first die.

Abstract: A transistor, including an antiferroelectric (AFE) gate dielectric layer is described. The AFE gate dielectric layer may be crystalline and include oxygen and a dopant. The transistor further includes a gate electrode on the AFE gate dielectric layer, a source structure and a drain structure on the substrate, where the gate electrode is between the source structure and the drain structure. The transistor further includes a source contact coupled with the source structure and a drain contact coupled with the drain structure.

Abstract: An electronic package and a manufacturing method thereof are provided, where a plurality of shielding wires are arranged on a carrier and spanning across an electronic component to cover the electronic component, so that the shielding wires serve as a shielding structure to protect the electronic component from the interference of external electromagnetic waves.

Abstract: The present application provides a method for preparing a semiconductor package The method includes bonding a bottom device die onto a package substrate; attaching a top device die onto the bottom device die; attaching an additional package substrate onto the top device die; establishing electrical connection between the additional package substrate and the top device die, between the additional package substrate and the package substrate, and between the top device die and the package substrate; and encapsulating the bottom device die, the top device die and the additional package substrate by an encapsulant.