Patents Examined by Yu-Hsi D Sun
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Patent number: 12055821Abstract: Processing methods may be performed to form a pixel isolation structure on a semiconductor substrate. The method may include forming a pixel isolation bilayer on the semiconductor substrate. The pixel isolation bilayer may include a high-k layer overlying a stopping layer. The method may include forming a lithographic mask on a first region of the pixel isolation bilayer. The method may also include etching the pixel isolation bilayer external to the first region. The etching may reveal the semiconductor substrate. The etching may form the pixel isolation structure.Type: GrantFiled: November 20, 2020Date of Patent: August 6, 2024Assignee: Applied Materials, Inc.Inventors: Lan Yu, Benjamin D. Briggs, Tyler Sherwood, Zihao Yang
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Patent number: 12046624Abstract: A system is provided for time delay integration in complementary metal oxide semiconductor imaging sensors, the system comprising: a two dimensional parallel charge transfer structure comprising at least one column of CMOS Image sensor pinned photodiodes; each the diode in the column being connected to the next the diode by a two phase transfer gate, each the transfer gate having a barrier and a well configured such that a flow of charge in the column is unidirectional.Type: GrantFiled: November 21, 2018Date of Patent: July 23, 2024Assignee: BAE Systems Imaging Solutions Inc.Inventor: Robert Daniel McGrath
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Patent number: 12040235Abstract: A dummy gate electrode and a dummy gate dielectric are removed to form a recess between adjacent gate spacers. A gate dielectric is deposited in the recess, and a barrier layer is deposited over the gate dielectric. A first work function layer is deposited over the barrier layer. A first anti-reaction layer is formed over the first work function layer, the first anti-reaction layer reducing oxidation of the first work function layer. A fill material is deposited over the first anti-reaction layer.Type: GrantFiled: July 21, 2022Date of Patent: July 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ching Lee, Hsin-Han Tsai, Shih-Hang Chiu, Tsung-Ta Tang, Chung-Chiang Wu, Hung-Chin Chung, Hsien-Ming Lee, Da-Yuan Lee, Jian-Hao Chen, Chien-Hao Chen, Kuo-Feng Yu, Chia-Wei Chen, Chih-Yu Hsu
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Patent number: 12035563Abstract: A display device includes a display device including a substrate, and a display unit disposed on the substrate. An encapsulating unit encapsulates the display unit. The encapsulating unit includes a barrier organic layer. The barrier organic layer includes a plurality of organic materials and a plurality of inorganic materials. The inorganic materials are arranged in free volumes between the organic materials.Type: GrantFiled: January 4, 2023Date of Patent: July 9, 2024Assignees: SAMSUNG DISPLAY CO., LTD., IUCF-HYU (Industry-University Cooperation Foundation Hanyang University)Inventors: Seungyong Song, Hyojeong Kwon, Seunghun Kim, Myungmo Sung, Kwanhyuck Yoon
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Patent number: 12033957Abstract: In certain aspects, a three-dimensional (3D) memory device includes a plurality of channel structures in a first region, a staircase structure in a second region, and a word line extending in the first region and the second region. The first region and the second region are arranged along a first direction. The word line is discontinuous in the first direction between the first region and the second region.Type: GrantFiled: July 23, 2021Date of Patent: July 9, 2024Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Zhong Zhang, Di Wang, Wenxi Zhou
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Patent number: 12034024Abstract: There is provided a solid-state imaging device that is capable of suppression of color mixing caused by a pixel for near-infrared light and securement of a saturation charge amount of a pixel for visible light where the pixels are formed in a same substrate. The solid-state imaging device includes: a substrate; first to third photoelectric conversion units; infrared absorbing filters; first to third color filters; a first element isolation unit between the first and second photoelectric conversion units; and a second element isolation unit disposed between the second and third photoelectric conversion units, in which a cross-sectional area of the first element isolation unit along a direction in which the first and second photoelectric conversion units are aligned is larger than a cross-sectional area of the second element isolation unit along a direction in which the second and third photoelectric conversion units are aligned.Type: GrantFiled: July 12, 2019Date of Patent: July 9, 2024Assignee: Sony Semiconductor Solutions CorporationInventor: Yoshiki Ebiko
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Patent number: 12033958Abstract: A semiconductor device includes a substrate, semiconductor dies on the substrate, molding compound and a reinforcing layer suspended within the molding compound. The reinforcing layer may for example be a copper foil formed in the molding compound over the semiconductor dies during the compression molding process. The reinforcing layer may have a structural rigidity which provides additional strength to the semiconductor device. The reinforcing layer may also be formed of a thermal conductor to draw heat away from a controller die within the semiconductor device.Type: GrantFiled: November 29, 2021Date of Patent: July 9, 2024Assignee: Western Digital Technologies, Inc.Inventors: Yangming Liu, Shenghua Huang, Bo Yang, Ning Ye, Cong Zhang
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Patent number: 12027485Abstract: A method of forming a packaged semiconductor device includes attaching a backside surface of a semiconductor die to a major surface of a package substrate. A first conductive connector is formed over a portion of an active surface of the semiconductor die and a portion of the major surface of the package substrate. A first conductive connection between a first bond pad of the semiconductor die and a first substrate pad of the package substrate is formed by way of the first conductive connector. A bond wire connects a second bond pad of the semiconductor die to a second substrate pad of the package substrate. The first bond pad located between the second bond pad and an edge of the semiconductor die.Type: GrantFiled: August 29, 2022Date of Patent: July 2, 2024Assignee: NXP USA, Inc.Inventor: Jinbang Tang
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Patent number: 12029056Abstract: A display device having a long lifetime is provided. A large-sized display device is provided. A display device includes a first light-emitting device and a second light-emitting device. The first light-emitting device includes a hole-injection layer, a first light-emitting layer, and an electron-transport layer. The second light-emitting device includes a second light-emitting layer. The hole-injection layer contains a first compound and a second compound. The first light-emitting layer contains a third compound that emits light of a first color. The second light-emitting layer contains a fourth compound that emits light of a second color. The electron-transport layer contains a fifth compound. The first compound has a property of accepting electrons from the second compound. The second compound has a HOMO level higher than or equal to ?5.7 eV and lower than or equal to ?5.4 eV. The fifth compound has a HOMO level higher than or equal to ?6.Type: GrantFiled: February 14, 2020Date of Patent: July 2, 2024Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Satoshi Seo, Harue Osaka
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Patent number: 11990576Abstract: An optoelectronic semiconductor device may include a first semiconductor layer and a second semiconductor layer, the first and second semiconductor layers being stacked one above the other. The device may include a first contact structure and a contact layer. The device may include a separating layer arranged over a side of the contact layer, and a current spreading layer arranged over a side of the separating layer facing away from the contact layer. The first contact structure may be connected to the contact layer via the current spreading layer and the separating layer. A layer stack may include the contact layer, the separating layer, and the current spreading layer has an anisotropic conductivity. The separating layer is present as a continuous layer in a region between the contact layer and the current spreading layer.Type: GrantFiled: January 8, 2020Date of Patent: May 21, 2024Assignee: OSRAM Opto Semiconductors GmbHInventor: Franz Eberhard
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Patent number: 11984428Abstract: Apparatuses and methods for coupling semiconductor devices are disclosed. Terminals (e.g., die pads) of a plurality of semiconductor devices may be coupled in a daisy chain manner through conductive structures that couple one or more terminals of a semiconductor device to two conductive bond pads. The conductive structures may be included in a redistribution layer (RDL) structure. The RDL structure may have a āUā shape in some embodiments of the disclosure. Each end of the āUā shape may be coupled to a respective one of the two conductive bond pads, and the terminal of the semiconductor device may be coupled to the RDL structure. The conductive bond pads of a semiconductor device may be coupled to conductive bond pads of other semiconductor devices by conductors (e.g., bond wires). As a result, the terminals of the semiconductor devices may be coupled in a daisy chain manner through the RDL structures, conductive bond pads, and conductors.Type: GrantFiled: December 8, 2022Date of Patent: May 14, 2024Assignee: Micron Technology, Inc.Inventors: Matthew B. Leslie, Timothy M. Hollis, Roy E. Greeff
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Patent number: 11978825Abstract: Methods and structures for forming arrays of LED devices are disclosed. The LED devices in accordance with embodiments of the invention may include an internally confined current injection area to reduce non-radiative recombination due to edge effects. Several manners for confining current may include etch removal of a current distribution layer, etch removal of a current distribution layer and active layer followed by mesa re-growth, isolation by ion implant or diffusion, quantum well intermixing, and oxide isolation.Type: GrantFiled: July 29, 2021Date of Patent: May 7, 2024Assignee: Apple Inc.Inventors: Kelly McGroddy, Hsin-Hua Hu, Andreas Bibl, Clayton Ka Tsun Chan, Daniel Arthur Haeger
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Patent number: 11973079Abstract: Various embodiments of the present disclosure are directed towards a method for forming a semiconductor structure. The method includes forming a stack of semiconductor layers comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers over a semiconductor substrate. A first stack of masking layers is formed over the stack of semiconductor layers with a first width and a second stack of masking layers is formed laterally offset from the stack of semiconductor layers with a second width less than the first width. A patterning process is performed on the semiconductor substrate and the stack of semiconductor layers, thereby defining a first fin structure laterally adjacent to a second fin structure. The first fin structure has the first width and the second fin structure has the second width. The stack of semiconductor layers directly overlies the first fin structure and has the first width.Type: GrantFiled: May 19, 2022Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chih-Chao Chou, Chih-Hao Wang, Shi Ning Ju, Kuo-Cheng Chiang, Wen-Ting Lan
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Patent number: 11967632Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack is formed comprising vertically-alternating first tiers and second tiers above the conductor tier. The stack comprises laterally-spaced memory-block regions having horizontally-elongated trenches there-between. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from that of the second tiers. A lowest of the first tiers is thicker than the first tiers there-above. The first-tier material is isotropically etched selectively relative to the second-tier material to form void-space in the first tiers. Conducting material is deposited into the trenches and into the void-space in the first tiers. The conducting material fills the void-space in the first tiers that are above the lowest first tier.Type: GrantFiled: August 18, 2021Date of Patent: April 23, 2024Inventor: John D. Hopkins
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Patent number: 11961778Abstract: A semiconductor device package includes a substrate having a top planar surface and a first semiconductor die electrically connected to the top planar surface of the substrate. The first semiconductor die and substrate define a tunnel and a first molding compound encapsulates the first semiconductor die and fills the tunnel. A second molding compound that is separate and distinct from the first molding compound is mounted on a top surface of the first molding compound. The first molding, when in a flowable state, has a viscosity that is lower than a viscosity of the second molding compound when it is in a flowable state.Type: GrantFiled: September 27, 2021Date of Patent: April 16, 2024Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.Inventors: Shenghua Huang, Yangming Liu, Bo Yang, Ning Ye
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Patent number: 11956987Abstract: The present application discloses a display panel and a preparation method thereof, and a display device. The display panel includes a base substrate, and has a display area, a peripheral area surrounding the display area, a hole area located at the display area, and an isolation area located between the hole area and the display area. The display area includes an electroluminescent device located on the base substrate, and a packaging structure for sealing the electroluminescent device, the packaging structure includes an inorganic packaging layer and an organic packaging layer alternately stacked, and the inorganic packaging layer extends to the hole area. The isolation area includes an organic layer located on the inorganic packaging layer.Type: GrantFiled: March 29, 2021Date of Patent: April 9, 2024Assignees: Chongqing BOE Display Technology Co., Ltd., BOE Technology Group Co., Ltd.Inventors: Qiang Zhang, Xiaoge Wang, Jiabin Cui
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Patent number: 11955435Abstract: A semiconductor package includes a semiconductor die and an encapsulant layer. A mark is formed on a surface of the encapsulant layer. A damage barrier layer is disposed between the mark and the semiconductor die. The damage barrier layer blocks the propagation of laser light used to form the mark from reaching the semiconductor die.Type: GrantFiled: December 29, 2021Date of Patent: April 9, 2024Assignee: SK hynix Inc.Inventor: Ki Yong Lee
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Patent number: 11948859Abstract: An element module includes a cooler, a plurality of elements, and a conductive member. The cooler includes a first element disposition portion and a second element disposition portion which are provided on both sides in a predetermined direction. The plurality of elements are disposed in each of the first element disposition portion and the second element disposition portion. The conductive member is disposed in a space portion of the cooler. The space portion penetrates the cooler between the plurality of elements in each of the first element disposition portion and the second element disposition portion. The space portion allows the first element disposition portion and the second element disposition portion to communicate with each other. The conductive member is connected to the element of the first element disposition portion and the element of the second element disposition portion.Type: GrantFiled: December 5, 2019Date of Patent: April 2, 2024Assignee: TOSHIBA MITSUBISHI-ELECTRIC INDUSTRIAL SYSTEMS CORPORATIONInventors: Takayuki Furuya, Akira Kagami
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Patent number: 11942455Abstract: Stacked semiconductor dies for semiconductor device assemblies and associated methods and systems are disclosed. In some embodiments, the semiconductor die assembly includes a substrate with a first opening in an inner portion and a second opening in an outer portion of the substrate. Further, the semiconductor die assembly can include a master die attached to a front side of the substrate, where the master die includes a first bond pad proximate to the first opening and a second bond pad proximate to the second opening. The first and second bond pads of the master die can be coupled with first and second substrate bond pads on a back side of the substrate, opposite to the front side, using first and second bonding wires extending through the first and second openings, respectively.Type: GrantFiled: May 11, 2022Date of Patent: March 26, 2024Assignee: Micron Technology, Inc.Inventors: Yeongbeom Ko, Youngik Kwon, Jong Sik Paek, Jungbae Lee
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Patent number: 11942402Abstract: An isolator device includes a laminate die having a dielectric laminate material with a metal laminate layer on one side of the dielectric laminate material, the metal laminate layer being a patterned layer providing at least a first plate, including a dielectric layer over the first plate that includes an aperture exposing a portion of the first plate. An integrated circuit (IC) including a substrate having a semiconductor surface includes circuitry including a transmitter and/or a receiver, the IC including a top metal layer providing at least a second plate coupled to a node in the circuitry, with at least one passivation layer on the top metal layer. A non-conductive die attach (NCDA) material for attaching a side of the dielectric laminate material is opposite the metal laminate layer to the IC so that the first plate is at least partially over the second plate to provide a capacitor.Type: GrantFiled: February 23, 2022Date of Patent: March 26, 2024Assignee: Texas Instruments IncorporatedInventor: Thomas Dyer Bonifield