Abstract: A communication unit (S1, S2) for industrial automation for use in a communication system (10) of series-connected communication units (M, S1, S2). The communication unit includes a first input (E1) and a first output (A1) and being configured to receive, via the input (E1), an input serial data stream having payload data and to output, via the output (A1), an output serial data stream (ADS) having payload data. The communication unit (S1, S2) is configured to determine clock information (TI) on the basis of an internal reference clock signal of the communication unit (S1, S2) and an input symbol clock of the input data stream and, using the clock information (TI), to provide the output data stream (ADS) with an output symbol clock whose clock rate is equal to the clock rate of the input symbol clock.

Abstract: A fail-safe power limit (FSPL) can be applied to components that lose communication with a management module (MM) to determine a safe power level at which to operate. The FSPL may be computed by the management module (MM) for the information handling system and distributed to components in the information handling system. By computing a FSPL and transmitting the FSPL to the components, a larger amount of the available power can be used by the components. This allows the components to continue operating at performance levels closer to or equivalent to levels available when the management module (MM) is operating normally. The FSPL may be updated at set times and/or on a periodic schedule such that the FSPL used by the components when communication is lost with the management module (MM) reflects a recent operating state of the components.

Abstract: Method for activating a feature of a chip having an interface comprising at least two power pins. The method comprises the following steps: the chip measures a series of voltage values between said power pins, the chip detects a series of sync signals different from clock signals, said sync signals being interleaved with said voltage values, the chip identifies a data sequence from said series of voltage values, and the chip activates the feature only if the data sequence matches a predefined pattern.

Abstract: During a power-on self-test (POST), a basic input/output system (BIOS) retrieves an attribute value associated with the persistent memory device, and compares the attribute value to a default value. In response to the attribute value matching the default value, the BIOS may determine that a firmware management protocol was not executed during a previous POST. In response to the attribute value not matching the default value, the BIOS may compare the attribute value to a current firmware version of firmware within the persistent memory device.

Abstract: The disclosure is related to a method and a system for security verification in a booting process of a computer system. A multi-core processor of the computer system is utilized to perform a security verification operation initiated by a UEFI BIOS. The security verification operation is configured to test if the computer system is qualified as a secure system for a specific use. In one aspect, the multi-core processor architecture has the benefit of providing a more efficient way to allow each of the multiple cores to perform one verification task for one of the peripherals of the system. An embodiment shows that the multiple cores can be individually assigned to perform different tasks such as verifying security of various medium in parallel processes when the computer system is in the booting process.

Abstract: Embodiments include an autonomous core perimeter, configured to save the state of a core of a multi-core processor prior to the processor package being placed into a low-power state. The autonomous core perimeter of each core is configured to save an image of a microcontroller firmware to an external store if it has not been previously saved by another core, along with the unique working state information of that core's microcontroller. Upon restore, the single microcontroller firmware image is retrieved from the external store and pushed to each core along with each core's unique working state.

Abstract: An information handling system operating a performance optimization system may comprise a processor executing computer program code instructions that interact with a plurality of computer operations and that is configured for iteratively sampling field performance data of the information handling system during learning windows having a preset duration and occurring at a preset frequency according to optimal learning window parameters, and adjusting the performance of the information handling system via adjustment of optimized system configurations based on application of a predetermined statistical model to the iteratively sampled field performance data. The optimal learning window parameters may be determined based on accuracy of previous application of the predetermined statistical model to test performance data of the information handling system.

Abstract: The present disclosure relates to an apparatus and method for improving thermal cycling reliability of a multicore microprocessor, and a method for a method for improving thermal cycling reliability of a multicore microprocessor according to an embodiment of the present disclosure includes determining an optimal temperature of a microprocessor to maximize a mean time to failure of the microprocessor, and increasing at least one of an operating frequency of the microprocessor or a processor utilization of the microprocessor to make a temperature of the microprocessor equal to or higher than the optimal temperature.

Abstract: A system provided for configuring settings of a device installed in a vehicle based on a user's personal attributes. The system includes an inference module that dynamically gathers one or more personal attributes of the user, and a control unit that applies a configuration to the device based on the personal attributes.

Abstract: A parallel multi-step power management flow apparatus and method for using the same are disclosed. In one embodiment, an integrated circuit comprises a plurality of processing entities to execute operations, a power controller coupled to the plurality of processing entities to control power management for the plurality of processing entities, and a plurality of agents, where each of the plurality of agents is operable to perform a power control flow for one of the processing entities by separately scheduling, using a scheduler, and executing a plurality of power control flow phases in response to a plurality of requests received from the power controller, and each agent is operable to send a plurality of acknowledgements, one acknowledgement for each phase, upon completion of the plurality of power control flow phases.

Abstract: A computing device includes main volatile memory and a node. The node includes a central processing module, non-volatile memory; and a non-volatile memory interface unit. A combination of the non-volatile memory and the main volatile memory stores an application specific operating system and at least a portion of a computing device operating system. The application specific operating system includes a plurality of application specific system level operations and the computing device operating system includes a plurality of general system level operations. A first processing module of the central processing module operates in accordance with a selected operating system and ignores operation not included in the selected operating system. The selected operating system includes one or more selected application specific level operations of the application specific operating system.

Abstract: A method and system for clock synchronization in an electronic device based on time based control is disclosed. The method includes comparing a current value of a cumulative phase difference between a signal generated by a device clock and a reference signal, with a reset threshold. The method further includes generating a control value, when the current value is greater than the reset threshold. Generating the control value includes computing a startup correction value based on a time lapsed after reset of the device clock, a dynamic correction value based on an accuracy factor, a clock constant, and a comparison of a current phase difference between with a high error threshold, and computing the control value based on the startup correction value, the dynamic correction value, and the current value of the cumulative phase difference. The method includes adjusting a frequency of the device clock based on the control value.

Abstract: In an embodiment, a processor includes a plurality of cores to independently execute instructions, a shared cache coupled to the cores and including a plurality of lines to store data, and a power controller including a low power control logic to calculate a flush latency to flush the shared cache based on a state of the plurality of lines. Other embodiments are described and claimed.

Abstract: A technique establishes a powered link over a transmission line. The technique includes, after determination of a power level to be provided to a powered device coupled to the transmission line, providing an output signal having a power-saving signal level to the transmission line until detecting an event. The event may be a power-up or a disconnect of the powered device. The technique may further include changing the output signal from the power-saving signal level to the powered-mode output signal level. The technique may include providing the powered-mode output signal level until detecting a disconnect of the powered device. The technique may include providing a second output signal to an additional powered device coupled to an additional transmission line until detecting the event. The technique may include changing the second output signal from the power-saving signal level to a second powered-mode output signal level synchronous with changing the output signal.

Abstract: A storage device includes nonvolatile memory devices that store data, a storage controller, and an adaptive power supply circuit. The storage controller controls the nonvolatile memory devices. The adaptive power supply circuit generates at least one operation voltage based on at least one power supply voltage, and provides the at least one operation voltage to the nonvolatile memory devices and the storage controller. The at least one power supply voltage is provided to the adaptive power supply circuit through a portion of power lines connected to a host. Under control of the storage controller, the adaptive power supply circuit adaptively activates a power disable function associated with a provision of the at least one operation voltage according to a level of a third power supply voltage provided through a third power line of the plurality of power lines. The third power supply voltage is provided by the host.

Abstract: A method comprises a system comprising a host device coupled to a first remote device actively operating according to a state diagram that the host device and all remote devices follow during operation of the system. The method further comprises powering up a second remote device while the host device and first remote device are actively operating according to the state diagram. The second remote device waits for a synchronization point sequence. Upon detecting the synchronization point sequence, the second remote device implements a predetermined feature set and synchronizes itself to the state diagram at a common point as the host device and first remote device.

Abstract: A power management integrated circuit (PMIC) capable of operating, in memory systems, as a master control in power management in some situations and operating as a slave control in power management in other situations. For example, when used in a memory system operating on a SATA bus, the PMIC assumes the master control by monitoring the bus signals for entering or existing a sleep mode or a power shutdown mode, communicating to the controller of the memory system to prepare for the respective mode, and when ready, adjusting power states for the mode changes. For example, when used in a memory system operating on a PCIe bus, the PMIC assumes the slave control during a normal mode and a sleep mode, but the master control when the memory system is in a power disable mode in which the controller of the memory system is powered off.

Abstract: Various embodiments comprise a protective circuit to connect at least two voltage rails to each other upon detection of the loss of the supply voltage that provides input power to the voltage regulators. The protective circuit may cause the two outputs of the voltage regulators to be connected to each other through a resistor when such a loss occurs. This in turn may prevent possible circuit damage in the load by preventing the higher output voltage from dropping below the lower output voltage if the capacitors on the outputs of the voltage regulators discharge at different rates. Such a reverse-voltage condition might otherwise cause damage in the load circuitry.

Abstract: An automatic transfer switch for power over ethernet lighting and powered devices preferably includes at least one transfer switch module, a carrier board, a power supply and a housing. Each transfer switch module preferably includes a plurality of input transformers, a plurality of output transformers, a microcontroller, a power source equipment device, a power transfer device, a LAN Multiplexer and a PoE power monitor. The at least one transfer switch module is retained on the carrier board. The plurality of input transformers receive power and data inputs from power sourcing equipment. If a backup power switch detects a loss of power, a signal will be received by the microcontroller of the at least one transfer switch module. The microcontroller will instruct the power transfer device to supply electrical power to the plurality of output transformers. Data will also be supplied by the microcontroller to the LAN Multiplexer.

Abstract: A processor semiconductor chip is described. The processor semiconductor chip includes at least one processing core. The processor semiconductor chip also includes a memory controller. The processor semiconductor chip also includes an embedded non flash non-volatile random access memory having a stack of storage cells disposed above the processor semiconductor chip's semiconductor substrate. The embedded non-volatile random access memory is to store boot up program code that, when executed by the processor semiconductor chip, is to analyze a subsequent module of program code so that a maliciously modified version of the subsequent module of program code can be identified. The embedded non-volatile random access memory to also store the subsequent module of program code.