Abstract: A method that includes determining a first clock gap for a first block of an integrated circuit based on a performance factor of the first block or an external factor and adjusting a clock signal to the first block based on the first clock gap. The method also includes determining a second clock gap for a second block of the integrated circuit based on (i) the first clock gap and (ii) a performance factor of the second block or the external factor. The second clock gap is different from the first clock gap. The method further includes adjusting the clock signal to the second block based on the second clock gap.

Abstract: Techniques in electronic systems, such as in systems including a processing chip and one or more external memory chips, provide improvements in one or more of system security (such as intrusion and/or virus/malware prevention), performance, cost, and efficiency. For example, the processing chip includes at least one CPU and circuitry enabling the at least one CPU to securely boot from an external, non-volatile memory chip containing encrypted, executable code, and does not expose un-encrypted data, including the executable code, on an external memory interface, including a DRAM interface. Further, only the specific processing chip that was used to initially write the encrypted executable code to the external non-volatile memory chip is able to decrypt the encrypted executable code. The decryption uses a key unique to the processing chip and created at manufacturing time that is never CPU-accessible, forming a secure hardware association between the two chips.

Abstract: A module may have more than one device, such as an IoT device, that requires bootstrapping. A first device may be provisioned with a pre-shared key (PSK). The first device, such as an IoT device, may bootstrap in a conventional manner using its PSK. A second device without a PSK may be added to the module post-manufacture. The first device may share registration details with the second device and also with an LwM2M server. When contacted by the second device, the LwM2M server may associate the second device with the first device and treat them as one from an operational standpoint, reducing the need for pre-shared keys across domains lacking an existing trust relationship.

Abstract: An industrial internet of things gateway boot method is described wherein installation, operation and maintenance phases are controlled to limit the chance of a malicious attack on a connected network.

Abstract: A method may include, in an operating system, implementing a sensor hub in firmware of a platform controller hub of an information handling system, the sensor hub configured to implement a plurality of sensor physical microdrivers, each of the plurality of sensor physical microdrivers corresponding to a respective sensor of a plurality of sensors and configured to communicate a signal representing a physical quantity sensed by the respective sensor; a plurality of algorithm microdrivers implemented as virtual microdrivers, each of the plurality of algorithm microdrivers corresponding to a respective sensor physical microdriver of the plurality of sensor physical microdrivers; and a user-awareness arbitration microdriver implemented as a virtual microdriver and configured to receive an arbitration policy for user awareness detection, receive sensor information from the plurality of algorithm microdrivers, and based on the arbitration policy, apply arbitration logic to the sensor information to determine a user

Abstract: The present disclosure describes methods, devices, and storage mediums for adjusting computing resource. The method includes obtaining an expected pooling time of a target pooling layer and a to-be-processed data volume of the target pooling layer; obtaining a current clock frequency corresponding to at least one computing resource unit used for pooling; determining a target clock frequency according to the expected pooling time of the target pooling layer and the to-be-processed data volume of the target pooling layer; and in response to that the convolution layer associated with the target pooling layer completes convolution and the current clock frequency is different from the target clock frequency, switching the current clock frequency of the at least one computing resource unit to the target clock frequency, and performing pooling in the target pooling layer based on the at least one computing resource unit having the target clock frequency.

Abstract: Apparatuses, systems, and methods for distributing a global counter value in a multi-socket SoC complex. In exemplary aspects, an apparatus comprises a first system-on-a-chip (SoC) in a first socket and a second SoC in a second socket. The apparatus further comprises a reset circuit coupled to the first SoC and the second SoC, a reset synchronization circuit coupled to the reset circuit, the first SoC, and the second SoC, and a global counter clock signal coupled to the reset synchronization circuit, the first SoC, and the second SoC. The reset synchronization circuit is configured to generate a global counter reset signal in response to a reset signal received from the reset circuit and to distribute the global counter reset signal to the first SoC and the second SoC substantially simultaneously.

Abstract: The present invention relates to a securing boot controller for an embedded system, the embedded system further comprising an operational module incorporating an operational function of the system, and a verification module incorporating a function of verifying various components of the system; The controller is configured to: upon cold startup of the system, make the verification function executable at boot up to perform a functional verification including a verification of the authenticity and integrity of the operational function; upon successful completion of the functional verification, at each warm start following said cold start of the system, making the operational function executable at boot up.

Abstract: An information handling system may include at least one processor; and a computer-readable medium having instructions thereon that are executable by the at least one processor for: prior to initialization of an operating system, executing a pre-boot environment; and within the pre-boot environment, downloading a universal filesystem driver from a first back-end server and loading the universal filesystem driver in the pre-boot environment, wherein the universal filesystem driver is a single pre-boot firmware volume that comprises drivers for a plurality of different filesystems.

Abstract: A system and method for energy conservation in a virtual universe, the method comprising: determining, at a server, available energy conservation options associated with an avatar of the virtual universe; determining, at the server, selected energy conservation options of the available energy conservation options; and applying, at the server, the selected energy conservation options to portions of the virtual universe associated with the avatar.

Abstract: A power-availability-based power delivery configuration system includes a power scaling system that is coupled to a device and a power system. The power scaling system includes an adjustable power scaling circuit that is configured to convert power received from the power system from a first power level to a second power level. A power scaling controller is coupled to the device, the power system, and the power scaling circuit. The power scaling controller identifies a power amount available from the power system and, based on the power amount available from the power system, determines power delivery settings for the adjustable power scaling circuit and configures the adjustable power scaling circuit using the power delivery settings. The power scaling controller may also determine device settings for the device based on the power amount available from the power system and configure the device using the device settings.

Abstract: A method for handling input/output (I/O) expansion power faults in a telematics device is provided. The method includes setting an I/O expander power-off duration to an initial value and powering on an I/O expander interface. In response to detecting a power fault at the I/O expander interface, the I/O expander interface is powered-off dur the power-off duration and the power-off duration is increased. If the power-off duration is greater than the power-off duration limit, the I/O expander interface is permanently powered-off. The steps are repeated until either the power fault does not recur, or the I/O expander interface is permanently powered-off.

Abstract: Provided is an apparatus including a communication module including a processor and a communication unit; and an application module detachably coupled to the communication module, wherein the application module includes a functional unit including at least one of a sensor, an actuator, or a communication port that is to be connected to at least one of an external sensor or an external actuator, and an application module memory for storing firmware that is executed by the processor.

Abstract: A processing system includes a digital processing unit programmable as a function of a firmware stored to a non-volatile memory and a resource connected to the digital processing unit via a communication system. The processing system also includes a time reference circuit including a first digital counter circuit to generate, in response to a clock signal, a system time signal including a plurality of bits indicative of a time tick-count, and a time base distribution circuit to generate a time base signal by selecting a subset of the bits of the system time signal, wherein the time base signal is provided to the resource. The resource detects a given event, stores the time base signal to a register in response to the event, and signals the event to the digital processing unit. The digital processing unit reads, via the communication system, the time base signal from the register.

Abstract: In one embodiment, the present disclosure includes multichip timing synchronization circuits and methods. In one embodiment, hardware counters in different systems are synchronized. Programs on the systems may include synchronization instructions. A second system executes synchronization instruction, and in response thereto, synchronizes a local software counter to a local hardware counter. The software counter on the second system may be delayed a fixed period of time corresponding to a program delay on the first system. The software counter on the second system may further be delayed by an offset to bring software counters on the two systems into sync.

Abstract: A method of bootstrapping a device by a bootstrap server, the method comprising: receiving, at the bootstrap server from the device, bootstrap data to enable the bootstrap server to determine that the device is to be provisioned with a device account identifier; verifying, at the bootstrap server, that the device is eligible to obtain a device account identifier based on or in response to the bootstrap data; obtaining, at the bootstrap server, a device account identifier assigned to the device based on or in response to the determination that the device is eligible; provisioning, from the bootstrap server to the device, first credential data comprising the device account identifier assigned to the device.

Abstract: A semiconductor device includes a power supply; and a plurality of processor cores configured to operate with the power supply, wherein each of the plurality of processor cores includes a clock control circuit that decreases an own clock frequency used by an own processor core when detecting drop of a power supply voltage of the own processor core, and adjusts a speed at which the own clock frequency is increased according to a situation of a power supply voltage of another processor core among the plurality of processor cores.

Abstract: A technique for generating a customized program logic for booting a target system includes determining the hardware devices operatively connected with the target system. A list of identifiers of the determined hardware devices is sent to a server system. The server system selects from a set of drivers for each of the device identifiers in the list at least one driver operable to control the identified device to generate a sub-set of said set of drivers. The server system retrieves a core program logic being free of any drivers of the target system and sends the core program logic and the driver sub-set to the target system. The target system creates the customized program logic using the combination of the core program logic and the driver sub-set.

Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output a altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.

Abstract: An electronic apparatus and controlling method thereof is provided. The electronic apparatus includes a processor configured to, based on receipt of a command to execute an application, execute the application based on the boosting level information, based on a difference between a loading time according to the application being executed and a reference loading time being equal to or greater than a threshold value, identify another boosting level information of the electronic apparatus based on the reference loading time, and update the stored boosting level information to the identified other boosting level information.