Abstract: A peak power management (PPM) system is provided for managing peak power operations between two or more NAND memory dies. The PPM system includes a PPM circuit on each NAND memory die. Each PPM circuit includes a first pull-up driver electrically connected to a first power source and a first end of a PPM resistor; a second pull-up driver electrically connected to a second power source and a second end of the PPM resistor; a pull-down driver electrically connected to the second end of the PPM resistor; and a PPM contact pad connected to the second end of the PPM resistor. The PPM contact pads of the two or more NAND memory dies are electrically connected with each other with a common electric potential. The PPM system is configured to manage peak power operations according to the electric potential of the PPM contact pads.

Abstract: A distributed power network includes a power bus infrastructure distributed over a region with node points provided to interface with controllable power nodes. Each power node can be connected to an external power device such as a DC power source, a DC power load, or a rechargeable DC battery. The power nodes form a communication network and cooperate with each other to receive input power from DC power sources and or rechargeable DC batteries connected to the power bus infrastructure and distribute the power received therefrom to the power bus infrastructure for distribution to the DC power loads and to rechargeable DC batteries.

Abstract: A wakeup circuit includes an energy detection circuit and a wakeup signal generation circuit coupled to the energy detection circuit. The energy detection circuit is configured to, in response to receiving an input signal, generate a detect signal that is proportional to the input signal. The energy detection circuit is powered by the input signal. The wakeup signal generation circuit is configured to, in response to receiving the detect signal, generate a wakeup signal.

Abstract: A computer apparatus is provided, which includes a plurality of peripheral apparatuses, a non-volatile memory, a processor, and an authority-control circuit. The memory unit stores a plurality of boot codes and setting values of a function set of the peripheral apparatuses corresponding to each boot code, wherein the boot codes form a chain of trust. In response to the execution of a current boot code being completed, the authority-control circuit sets the setting values of the functions in a second function set corresponding to a next boot code in the chain of trust, sends an authority-control signal to control the peripheral apparatuses corresponding to the second function set according to the setting values of the functions in the second function set, and sets a boot flag corresponding to the next boot code in the authority-control circuit to control the processor to execute the next boot code.

Abstract: A memory controller having a data receiver to sample data at a sample timing using a strobe signal, wherein the data and the strobe signal are sent by a memory device in connection with a read operation initiated by the memory controller, and a strobe receiver to receive the strobe signal, wherein a phase of the strobe signal has a drift relative to a reference by an amount. The memory controller further having a monitoring circuit to monitor the strobe signal and determine the amount of the drift, and an adjustment circuit to update the sample timing of the data receiver based on the amount of drift determined by the monitoring signal.

Abstract: An asset includes physical computing resources and a physical computing resources manager. The physical computing resources manager obtains a power management update for a physical computing resource of the physical computing resources of the asset; in response to obtaining the power management update: obtains, using an out-of-band manager, a power management descriptor for the asset; updates the power management descriptor based on the power management update; stages the power management descriptor at a location; and performs a low resource consumption reboot using the location to implement the power management update.

Abstract: Method and systems support configuring components of a chassis comprising a plurality of IHSs (Information Handling Systems). A management controller of the chassis initiates a process for identifying a plurality of hardware and software capabilities of the chassis. Based on the identified capabilities, computing solutions, such as specialized computation and storage functions, supported by the chassis are determined. The computing solutions supported by the capabilities of the chassis are encoded, such as within a set of compatibility bits. Upon detecting updates to the hardware and software capabilities of the chassis, the encoded compatibility bits are used to determine compatibility of the updated capabilities with computing solutions supported by the chassis.

Abstract: An electronic device having a user interface for displaying battery usage of the device over a given time period. Suggestions to improve device battery life are displayed along with usage when battery savings suggestions criteria are met.

Abstract: Provided are an apparatus capable of generating a stream clock having the same frequency as a frequency in a normal mode, in a panel self-refresh mode and an embedded DisplayPort system including the same. The embedded DisplayPort system includes a stream clock generator. The stream clock generator may include an internal oscillator configured to oscillate an internal clock, a frequency regulator configured to compare frequencies of the internal clock and a link symbol clock, generate control signals, and adjust a frequency of the internal clock using the control signals, wherein the link symbol clock is reconstructed from stream data of the embedded DisplayPort system, and a phase-locked loop configured to generate a stream clock using the internal clock and lock a phase of the stream clock to a phase of the internal clock.

Abstract: This disclosure describes methods and systems to for a method for a first computing node to receive frequency information of a system clock. The first computing node receives the frequency information of the system clock from a second computing node at a physical layer of a connection between the first computing node and the second computing node. The first computing node also receives a message from the second computing node at above the physical layer of the connection between the first computing node and the second computing node. The message includes an attestation of the frequency information from which the first computing node may verify that the second computing node is a trusted source of the frequency information.

Abstract: In accordance with some embodiments, margining routines to determine acceptable voltage command values for specific CPU implementations at one or more different operating levels may be provided.

Abstract: The present disclosure provides a power management apparatus, method and system. The apparatus comprises: a client management module for configuring power management client module(s) on one or more clients, the power management client module being for power management of the client; a data collector module for collecting, via the power management client module(s), data related to the power management of one or more user accounts on one or more clients; and a repository module for storing the collected data.

Abstract: A wireless sensing system includes a power supply unit, a control unit, a backup power unit, and a wake-up unit. The control unit includes a microprocessor. The microprocessor acts according to a forced shutdown instruction and transmits the forced shutdown instruction to the wake-up unit through an internal control pin in order for the wake-up unit to generate a forced shutdown clock matching the forced shutdown instruction, transmit the forced shutdown clock to the power supply unit, and thereby stop the power supply unit from generating electricity, and for the backup power unit to transmit the electricity stored therein to the wake-up unit and thereby enable the wake-up unit to maintain its basic electrically driven functions. The backup power unit can supply a small amount of electricity to sustain the basic electrically driven functions of the system.

Abstract: Setting a power state of an information handling system, including identifying a power configuration policy, the power configuration policy including configuration rules for setting the power state of the information handling system; identifying a first power state of the information handling system; identifying, at a first time period, a first proximity of a communication-enabled portable computing device with respect to the information handling system; determining that the first proximity of the communication-enabled portable computing device is greater than a threshold; determining a velocity of movement of the communication-enabled portable computing device with respect to a receiver in communication with the communication-enabled portable computing device; accessing the power configuration policy to identify a configuration rule based on the velocity of movement of the communication-enabled portable computing device; and applying the particular configuration rule to adjust the first power state of the in

Abstract: The invention relates to a computer implemented method of generating multiple programs to deliver a computerised function, each program to be executed in a processing unit of a computer comprising a plurality of processing units each having instruction storage for holding a local program, an execution unit for executing the local program and data storage for holding data, a switching fabric connected to an output interface of each processing unit and connectable to an input interface of each processing unit by switching circuitry controllable by each processing unit, and a synchronisation module operable to generate a synchronisation signal, the method comprising: generating a local program for each processing unit comprising a sequence of executable instructions; determining for each processing unit a relative time of execution of instructions of each local program whereby a local program allocated to one processing unit is scheduled to execute with a predetermined delay relative to a synchronisation signal

Abstract: Systems, computing devices, and methods for authenticating privileged subsystem access by policy and by use of a security key generated at boot are disclosed herein. According to an aspect, a method includes generating a security key upon boot of a host-facing interface for a client. The method also includes communicating the security key to a baseboard management controller. Further, the method includes authenticating, to the host-facing interface commands, based on the security key. The method may also include implementing a policy associated with the security key. Further, in response to determining that a received command is not allowed by policy or the security key is not authenticated, an external server port or debug header may be disabled to prevent execution of the command.

Abstract: A system may include a power train comprising a rectifier and power factor correction stage configured to receive an alternating current (AC) input voltage waveform and convert the AC input voltage waveform into a regulated direct current (DC) voltage on a bulk capacitor configured to store electrical charge and a controller configured to control the rectifier and power factor correction stage to perform power factor correction between the AC input voltage waveform and an AC input current waveform related to the AC input voltage waveform. The controller may implement a voltage regulation loop configured to regulate the regulated DC voltage on the bulk capacitor to a desired constant average value based on a combination of a DC current signal associated with the power train and a voltage loop error signal based on the regulated DC voltage and a current loop regulating the shape of the AC input current waveform to a sinusoidal value in phase with the AC input voltage waveform.

Abstract: Disclosed aspects relate to a clock distribution network of a synchronous logic device. The synchronous logic device has sub-circuits having different clock domains. The clock domains form a hierarchical structure. The clock distribution network has a clock source to provide a global clock signal. A programmable delay line associated with a sub-circuit generates a local clock signal for the sub-circuit by delaying the signal. A global skew control circuit can manage clock skew between the local clock signals. The global skew control circuit may adjust a delay, determine initial operations for the delay lines, verify whether it is possible to perform the initial operations, and perform a correction operation. The correction operation can include correcting the control commands such that the corrected commands lead to the same change of skew adjustment between the local clocks.

Abstract: An apparatus includes a plurality of registers and a host interface comprising a plurality of pins. One of the plurality of registers may be a power state entry register configured to control entry to a low power state. One of the plurality of pins may be an enable pin. The apparatus may be configured to enter the low power state in response to setting the power state entry register to a first value and providing the enable pin a signal with a first level. The apparatus may be configured to exit the low power state in response to providing the enable pin the signal with a second level. The apparatus may enter an idle state after exiting the low power state. The low power state may consume less power than the idle state. The enable pin is implemented as an input configured to control a status of a plurality of regulators.

Abstract: An information handling system may include a host system comprising a host system processor, a management controller communicatively coupled to the host system processor and a logic device and configured to perform out-of-band management of the information handling system, and a logic device communicatively coupled to the host system and the management controller. The logic device may be configured to, upon determining that a watchdog timer has timed out a threshold number of times without completion of a boot of the management controller, allow boot of the host system, after boot of the host system, determine if a later boot of the management controller occurs, and if the later boot of the management controller occurs, force the host system to power off.