Abstract: A method is disclosed of removing a first material disposed over a second material adjacent to a field effect transistor gate having a gate sidewall layer that comprises an etch-resistant material on a gate sidewall. The method includes subjecting the first material to a gas cluster ion beam etch process to remove first material adjacent to the gate, and detecting exposure of the second material during the gas cluster ion beam (GCIB) etch process.

Abstract: A catalyst layer can be uniformly formed on an entire surface of a substrate and an entire inner surface of a recess. A catalyst layer forming method of forming the catalyst layer on the substrate includes a first supply processing of forming a substrate surface catalyst layer 22A by supplying a catalyst liquid on the entire surface of the substrate 2; and a second supply processing of forming a recess inner surface catalyst layer 22B by supplying the catalyst liquid to a central portion of the substrate 2 while rotating the substrate 2.

Abstract: Methods of fabricating MRAM devices are provided along with a processing apparatus for fabricating the MRAM devices. The methods may include forming a ferromagnetic layer, cooling the ferromagnetic layer to a temperature within a range of between about 50° K to about 300° K, forming and oxidizing one or more Mg layers on the cooled ferromagnetic layer to form an MgO structure, forming a free layer on the MgO structure, and forming a capping layer on the free layer.

Abstract: A FinFET device includes a semiconductor fin, a gate electrode extending over a channel of the fin and sidewall spacers on each side of the gate electrode. A dielectric material is positioned on each side of a bottom portion of said fin, with an oxide material on each side of the fin overlying the dielectric material. A recessed region, formed in the fin on each side of the channel region, is delimited by the oxide material. A raised source region fills the recessed region and extends from the fin on a first side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer. A raised drain region fills the recessed region and extends from the fin on a second side of the gate electrode to cover the oxide material to a height which is in contact with the sidewall spacer.

Abstract: A method of forming a rough surface includes: providing an article having a top surface, forming a plurality of agglomerated grains on the top surface by a deposition process, and patterning the top surface to form a rough surface by using the plurality of agglomerated grains as a mask.

Abstract: In connection with a semiconductor device including a capacitor element there is provided a technique capable of improving the reliability of the capacitor element. A capacitor element is formed in an element isolation region formed over a semiconductor substrate. The capacitor element includes a lower electrode and an upper electrode formed over the lower electrode through a capacitor insulating film. Basically, the lower electrode and the upper electrode are formed from polysilicon films and a cobalt silicide film formed over the surfaces of the polysilicon films. End portions of the cobalt silicide film formed over the upper electrode are spaced apart a distance from end portions of the upper electrode. Besides, end portions of the cobalt silicide film formed over the lower electrode are spaced apart a distance from boundaries between the upper electrode and the lower electrode.

Abstract: A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing either one of but not both of the top/bottom portion and the sidewall portion of the film by wet etching which removes the one of the top/bottom portion and the sidewall portion of the film more predominantly than the other according to the different chemical resistance properties.

Abstract: A method includes forming a first conductive feature positioned in a first dielectric layer. A conductive polymer layer is formed above the first dielectric layer and the first conductive feature. The conductive polymer layer has a conductive path length. A second dielectric layer is formed above the first dielectric layer. A first via opening is formed in the second dielectric layer and the conductive polymer layer to expose the first conductive feature. A conductive via is formed in the first via opening. The conductive via contacts the first conductive feature and the conductive polymer layer.

Abstract: A display device includes a substrate including an active region, a non-active region disposed outside the active region, and a driving region disposed on one side of the non-active region, gate lines disposed in the active region to extend in a row direction, data lines disposed in the active region to extend in a column direction, pixels connected to the gate lines and the data lines, repair wiring disposed in the non-active region, and a gate driving integrated circuit (“IC”) disposed in the driving region, the gate driving IC generating gate driving signals and transmitting the gate driving signals to the gate lines, where the repair wiring includes a first sub-repair line connected to the gate driving IC, and a second sub-repair line disposed in the non-active region to extend in the column direction, to be connected to the first sub-repair line, and to overlap the gate lines.

Abstract: A method of forming an oxide layer is provided in the present invention. The method includes the following steps. A first oxide layer is formed on a semiconductor substrate, and a quality enhancement process is then performed to etch the first oxide layer and densify the first oxide layer at the same time for forming a second oxide layer. The first oxide layer is etched and densified at the same time by a mixture of dilute hydrofluoric acid (DHF) and hydrogen peroxide (H2O2) in the quality enhancement process. The thickness of the second oxide layer may be reduced and the quality of the second oxide layer may be enhanced by the quality enhancement process at the same time.

Abstract: In a first aspect, the present disclosure provides a method of forming a semiconductor device, including providing an SOI structure comprising a base substrate, a buried insulating material layer formed on the base substrate and an active semiconductor layer formed on the buried insulating structure, forming a germanium-comprising layer on an exposed surface of the active semiconductor layer, forming a trench isolation structure, the trench isolation structure extending through the germanium-comprising layer and the active semiconductor layer, performing an annealing process after the trench isolation structure is formed, the annealing process resulting in an oxide layer disposed on a germanium-comprising active layer which is formed on the buried insulating material layer, and removing the oxide layer for exposing an upper surface of the germanium-comprising active layer.

Abstract: Technique includes forming a film containing first element, second element and carbon on a substrate by performing a cycle a predetermined number of times. The cycle includes non-simultaneously performing forming a first solid layer having thickness of more than one atomic layer and equal to or less than several atomic layers and containing chemical bonds of the first element and carbon by supplying a precursor having the chemical bonds to the substrate under a condition where the precursor is pyrolyzed and at least some of the chemical bonds contained in the precursor are maintained without being broken, and forming a second solid layer by plasma-exciting a reactant containing the second element and supplying the plasma-excited reactant to the substrate, or by plasma-exciting an inert gas and supplying the plasma-excited inert gas and a reactant containing the second element which is not plasma-excited to the substrate.

Abstract: The present disclosure provides a semiconductor package, including a first device having a first joining surface, a first conductive component at least partially protruding from the first joining surface, a second device having a second joining surface facing the first joining surface, and a second conductive component at least exposing from the second joining surface. The first conductive component and the second conductive component form a joint having a first beak. The first beak points to either the first joining surface or the second joining surface.

Abstract: Complementary high-voltage bipolar transistors formed in standard bulk silicon integrated circuits are disclosed. In one disclosed embodiment, collector regions are formed in an epitaxial silicon layer. Base regions and emitters are disposed over the collector region. An n-type region is formed under collector region by implanting donor impurities into a p-substrate for the PNP transistor and implanting acceptor impurities into the p-substrate for the NPN transistor prior to depositing the collector epitaxial regions. Later in the process flow these n-type and p-type regions are connected to the top of the die by a deep n+ and p+ wells respectively. The n-type well is then coupled to VCC while the p-type well is coupled to GND, providing laterally depleted portions of the PNP and NPN collector regions and hence, increasing their BVs.

Abstract: Two-terminal electronic devices, such as photodetectors, photovoltaic devices and electroluminescent devices, are provided. The devices include a first electrode residing on a substrate, wherein the first electrode comprises a layer of metal; an I-layer comprising an inorganic insulating or broad band semiconducting material residing on top of the first electrode, and aligned with the first electrode, wherein the inorganic insulating or broad band semiconducting material is a compound of the metal of the first electrode; a semiconductor layer, preferably comprising a p-type semiconductor, residing over the I-layer; and a second electrode residing over the semiconductor layer, the electrode comprising a layer of a conductive material. The band gap of the material of the semiconductor layer, is preferably smaller than the band gap of the I-layer material. The band gap of the material of the I-layer is preferably greater than 2.5 eV.

Abstract: Provided herein are approaches for patterning a semiconductor device. In an exemplary approach, a method includes providing a set of contact openings through a photoresist formed atop a substrate, and implanting ions into just a sidewall surface of the set of contact openings. In an exemplary approach, the ions are implanted at an implant angle nonparallel with the sidewall surface to prevent the ions from implanting a surface of the substrate within the set of contact openings, and to form a treated layer along an entire height of the contact opening. The method further includes etching the substrate within the set of contact openings after the ions are implanted into the sidewall surface. As a result, by using an angled ion implantation to the contact opening sidewall surface as a pretreatment prior to etching, local critical dimension uniformity is improved.

Abstract: A method for manufacturing a semiconductor light emitting device package includes forming a light emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer sequentially stacked on a growth substrate, forming a reflective layer on a first surface of the light emitting structure corresponding to a surface of the second conductivity-type semiconductor layer, forming bumps on the first surface, the bumps being electrically connected to the first or second conductivity-type semiconductor layer and protruding from the reflective layer, bonding a support substrate to the bumps on the first surface, removing the growth substrate, bonding a light transmissive substrate coated with a wavelength conversion layer to a second surface of the light emitting structure from which the growth substrate is removed, and removing the support substrate.

Abstract: In a microelectronic device, a substrate has first upper and lower surfaces. An integrated circuit die has second upper and lower surfaces. Interconnects couple the first upper surface of the substrate to the second lower surface of the integrated circuit die for electrical communication therebetween. A via array has proximal ends of wires thereof coupled to the second upper surface for conduction of heat away from the integrated circuit die. A molding material is disposed in the via array with distal ends of the wires of the via array extending at least to a superior surface of the molding material.

Abstract: A method of forming a semiconductor device that includes forming an in-situ doped semiconductor material on a semiconductor substrate, and forming fin structures from the in-situ doped semiconductor material. A sacrificial channel portion of the fin structures may be removed, wherein a source region and a drain region portion of the fin structures of the in-situ doped semiconductor material remain. The sacrificial channel portion of the fin structure may then be replaced with a functional channel region.

Abstract: A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.