Patents by Inventor Aaron Yip

Aaron Yip has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11029861
    Abstract: Memory devices might be configured to perform methods including reading a first page of memory cells and flag data wherein the flag data indicates whether a second page of memory cells adjacent to the first page is programmed, and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage; performing a sense operation on memory cells coupled to first data lines of a first array of memory cells and memory cells coupled to data lines of a second array of memory cells, and determining a program indication of memory cells coupled to second data lines from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells; and/or programming memory cells coupled to first data lines in a first array of memory cells, and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in a second array of memory cells with flag data indicative o
    Type: Grant
    Filed: August 19, 2019
    Date of Patent: June 8, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • Publication number: 20210151375
    Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.
    Type: Application
    Filed: December 28, 2020
    Publication date: May 20, 2021
    Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
  • Patent number: 11010976
    Abstract: An approach for simulating items in an environment, such as a room, is disclosed. A package file can store information including an image of the environment and metadata including an identifier that uniquely identifies a selected image. The package file can be used to regenerate a simulation of the item arranged over the image of the environment. Later changes can be made to the simulation of the item by accessing the metadata.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: May 18, 2021
    Assignee: Houzz, Inc.
    Inventors: Guy Shaviv, Xiaoyi Huang, Aaron Yip
  • Patent number: 10902927
    Abstract: Apparatus and methods are provided, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are provided.
    Type: Grant
    Filed: February 7, 2020
    Date of Patent: January 26, 2021
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Publication number: 20210005262
    Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first memory cell string; a second memory cell string; a first group of conductive lines to access the first and second memory cell strings; a second group of conductive lines; a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and a circuit including a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node, and a third transistor coupled between the second node and the common gate.
    Type: Application
    Filed: August 17, 2020
    Publication date: January 7, 2021
    Inventor: Aaron Yip
  • Patent number: 10879175
    Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: December 29, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Paolo Tessariol, Graham R. Wolstenholme, Aaron Yip
  • Patent number: 10847526
    Abstract: A microelectronic device comprises a stack structure having tiers each including a conductive structure and an insulating structure, the stack structure comprises a staircase region comprising staircase structures, a select gate contact region, and a memory array region between the staircase region and the select gate contact region; contact structures on steps of the staircase structures; string drivers coupled to the contact structures and comprising transistors underlying and within horizontal boundaries of the staircase region; a triple well structure underlying the memory array region; a select gate structure between the stack structure and the triple well structure; semiconductive pillar structures within horizontal boundaries of the memory array region and extending through the stack structure and the select gate structure to the triple well structure; and a select gate contact structure within horizontal boundaries of the select gate contact region and extending through the stack structure to the sele
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: November 24, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Patent number: 10846938
    Abstract: Disclosed are various embodiments for simulating one or more virtual objects (e.g., renders) specified spatial areas of a real-world environment. Options of item models for modeling in a given spatial area can be filtered based on specified dimensions and identified features of an image of a given spatial area. A selected item model can be rendered. and continuously updated on a display device as the client device is physical moved.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: November 24, 2020
    Assignee: Houzz, Inc.
    Inventor: Aaron Yip
  • Publication number: 20200357468
    Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.
    Type: Application
    Filed: July 6, 2020
    Publication date: November 12, 2020
    Inventor: Aaron Yip
  • Publication number: 20200321064
    Abstract: Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.
    Type: Application
    Filed: February 7, 2020
    Publication date: October 8, 2020
    Inventor: Aaron Yip
  • Patent number: 10755460
    Abstract: A flat scene modeler can more accurately simulate items in environments by receiving instructions to model a given 2D depiction of an item in a given 2D depiction of a room. The flat scene modeler can analyze the instructions and arrange a 3D model of the item in a 3D model of the room. Textures, materials, lighting, and virtual camera position are modified per the received instructions. Two-dimensional images rendered from the 3D models can be provided to a user as a simulation.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: August 25, 2020
    Assignee: Houzz, Inc.
    Inventors: Xiaoyi Huang, Aaron Yip
  • Patent number: 10748620
    Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a first memory cell string; a second memory cell string; a first group of conductive lines to access the first and second memory cell strings; a second group of conductive lines; a group of transistors, each transistor of the group of transistors coupled between a respective conductive line of the first group of conductive lines and a respective conductive line of the second group of conductive lines, the group of transistors having a common gate; and a circuit including a first transistor and a second transistor coupled in series between a first node and a second node, the first transistor including a gate coupled to the second node, and a third transistor coupled between the second node and the common gate.
    Type: Grant
    Filed: March 22, 2018
    Date of Patent: August 18, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Patent number: 10741259
    Abstract: Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Toru Tanzawa, Aaron Yip
  • Patent number: 10706930
    Abstract: Some embodiments include apparatuses, and methods of operating the apparatuses. Some of the apparatuses include a data line, a first memory cell string including first memory cells located in different levels of the apparatus, first access lines to access the first memory cells, a first select gate coupled between the data line and the first memory cell string, a first select line to control the first select gate, a second memory cell string including second memory cells located in different levels of the apparatus, second access lines to access the second memory cells, the second access lines being electrically separated from the first access lines, a second select gate coupled between the data line and the second memory cell string, a second select line to control the second select gate, and the first select line being in electrical contact with the second select line.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: July 7, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Publication number: 20200126288
    Abstract: An object can be simulated in an environment using a three-dimensional model of the object as viewed from a virtual camera at a position in the environment. The position in the environment can he determined using user input or through visual analysis of a video recording. Composite frames depicting the modeled object may be played back based on the orientation of the playback device.
    Type: Application
    Filed: September 26, 2019
    Publication date: April 23, 2020
    Inventors: Xiaoyi Huang, Aaron Yip
  • Publication number: 20200105066
    Abstract: Disclosed are various embodiments for simulating one or more virtual objects (e.g., renders) specified spatial areas of a real-world environment. Options of item models for modeling in a given spatial area can be filtered based on specified dimensions and identified features of an image of a given spatial area. A selected item model can be rendered. and continuously updated on a display device as the client device is physical moved.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 2, 2020
    Inventor: Aaron Yip
  • Patent number: 10593624
    Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: March 17, 2020
    Assignee: Intel Corporation
    Inventors: Deepak Thimmegowda, Aaron Yip, Mark Helm, Yongna Li
  • Publication number: 20200051338
    Abstract: Embodiments of the present invention, as presented herein, relate to an augmented reality application-based service, which facilitates the sharing of a design request, by a first end-user, via a messaging application or social networking service. The design request may be included as part of a content posting published to a feed and shared with members of a social networking service, and enables the members to select and position products (e.g., images of household items) using a room design application, such that the selected and positioned products can be rendered in a live AR viewing session by the first end-user.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 13, 2020
    Inventors: Khurram Mahmood Zia, Sanjay Raman, Aaron Yip
  • Patent number: 10559367
    Abstract: Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then he applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: February 11, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Publication number: 20190369887
    Abstract: Memory devices might be configured to perform methods including reading a first page of memory cells and flag data wherein the flag data indicates whether a second page of memory cells adjacent to the first page is programmed, and determining from the flag data whether to re-read the first page of memory cells with an adjusted read voltage; performing a sense operation on memory cells coupled to first data lines of a first array of memory cells and memory cells coupled to data lines of a second array of memory cells, and determining a program indication of memory cells coupled to second data lines from the sense operation performed on the memory cells coupled to the data lines of the second array of memory cells; and/or programming memory cells coupled to first data lines in a first array of memory cells, and programming memory cells coupled to second data lines in the first array of memory cells while programming memory cells coupled to data lines in a second array of memory cells with flag data indicative o
    Type: Application
    Filed: August 19, 2019
    Publication date: December 5, 2019
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler