Patents by Inventor Aaron Yip

Aaron Yip has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Apparatuses and methods using dummy cells programmed to different states
    Patent number: 9697907
    Abstract: Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: July 4, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Toru Tanzawa, Aaron Yip
  • REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES
    Publication number: 20170178738
    Abstract: Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then he applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.
    Type: Application
    Filed: March 6, 2017
    Publication date: June 22, 2017
    Inventor: Aaron Yip
  • Semiconductor devices including stair step structures, and related methods
    Patent number: 9659950
    Abstract: Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed.
    Type: Grant
    Filed: October 8, 2015
    Date of Patent: May 23, 2017
    Assignee: MICRON TECHNOLOGY, INC.
    Inventors: Aaron Yip, Qiang Tang, Chang Wan Ha
  • Three dimensional memory control circuitry
    Patent number: 9620229
    Abstract: An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: April 11, 2017
    Assignee: Intel Corporation
    Inventors: Mark Helm, Jung Sheng Hoei, Aaron Yip, Dzung Nguyen
  • SENSE OPERATION FLAGS IN A MEMORY DEVICE
    Publication number: 20170075613
    Abstract: In a memory device, odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. Even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
    Type: Application
    Filed: November 3, 2016
    Publication date: March 16, 2017
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • Reducing programming disturbance in memory devices
    Patent number: 9589644
    Abstract: Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: March 7, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Sense operation flags in a memory device
    Patent number: 9519582
    Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: December 13, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • APPARATUSES AND METHODS USING DUMMY CELLS PROGRAMMED TO DIFFERENT STATES
    Publication number: 20160343446
    Abstract: Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.
    Type: Application
    Filed: August 3, 2016
    Publication date: November 24, 2016
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Toru Tanzawa, Aaron Yip
  • Apparatuses and methods using dummy cells programmed to different states
    Patent number: 9412451
    Abstract: Apparatuses and methods for reducing capacitive loading are described. An example apparatus may include a plurality of memory subblocks of a memory block. A plurality of word lines may be associated with the plurality of subblocks. The word lines may be further associated with multiple strings within the subblocks. A subset of the word lines may be dummy word lines. The cells of the dummy word lines may be programmed to a plurality of states. The states may be configured to deactivate and/or float unselected strings in the subblocks during certain memory operations.
    Type: Grant
    Filed: October 8, 2014
    Date of Patent: August 9, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Toru Tanzawa, Aaron Yip
  • THREE DIMENSIONAL MEMORY CONTROL CIRCUITRY
    Publication number: 20160196879
    Abstract: An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.
    Type: Application
    Filed: October 29, 2015
    Publication date: July 7, 2016
    Inventors: MARK HELM, JUNG SHENG HOEI, AARON YIP, DZUNG NGUYEN
  • APPARATUSES AND METHODS USING DUMMY CELLS PROGRAMMED TO DIFFERENT STATES
    Publication number: 20160104533
    Abstract: Apparatuses and methods for reducing capacitive loading are described. An example apparatus may include a plurality of memory subblocks of a memory block. A. plurality of word lines may be associated with the plurality of subblocks. The word lines may be further associated with multiple strings within the subblocks. A subset of the word lines may be dummy word lines. The cells of the dummy word lines may be programmed to a plurality of states. The states may be configured to deactivate and/or float unselected strings in the subblocks during certain memory operations.
    Type: Application
    Filed: October 8, 2014
    Publication date: April 14, 2016
    Inventors: TORU TANZAWA, Aaron Yip
  • SEMICONDUCTOR DEVICES INCLUDING STAIR STEP STRUCTURES, AND RELATED METHODS
    Publication number: 20160027793
    Abstract: Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed.
    Type: Application
    Filed: October 8, 2015
    Publication date: January 28, 2016
    Inventors: Aaron Yip, Qiang Tang, Chang Wan Ha
  • Single check memory devices and methods
    Patent number: 9236146
    Abstract: Memory devices and methods of operating memory devices are shown. Configurations described include circuits to perform a single check between programming pulses to determine a threshold voltage with respect to desired benchmark voltages. In one example, the benchmark voltages are used to change a programming speed of selected memory cells.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: January 12, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Aaron Yip, Tomoharu Tanaka
  • SENSE OPERATION FLAGS IN A MEMORY DEVICE
    Publication number: 20150363313
    Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
    Type: Application
    Filed: August 24, 2015
    Publication date: December 17, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • Three dimensional memory control circuitry
    Patent number: 9202536
    Abstract: An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: December 1, 2015
    Assignee: Intel Corporation
    Inventors: Mark Helm, Jung Sheng Hoei, Aaron Yip, Dzung Nguyen
  • Semiconductor devices including stair step structures, and related methods
    Patent number: 9165937
    Abstract: Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Aaron Yip, Qiang Tang, Chang Wan Ha
  • Sense operation flags in a memory device
    Patent number: 9135998
    Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: September 15, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • Methods and devices for memory reads with precharged data lines
    Patent number: 9099189
    Abstract: Methods of operating memory devices including precharging an adjacent pair of data lines to a particular voltage, isolating one data line of the adjacent pair of data lines from the particular voltage while maintaining the other data line of the adjacent pair of data lines at the particular voltage, and selectively discharging the one data line depending upon a data value of a selected memory cell of a string of memory cells associated with the one data line.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: August 4, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Erase operation control sequencing apparatus, systems, and methods
    Patent number: 9070459
    Abstract: Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: June 30, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Xiaojun Yu, Jin-man Han, Aaron Yip
  • SYSTEMS WITH MEMORY SEGMENTATION AND SYSTEMS WITH BIASING LINES TO RECEIVE SAME VOLTAGES DURING ACCESSING
    Publication number: 20150103578
    Abstract: Memory devices, memory arrays, and methods of operation of memory arrays with segmentation. Segmentation elements can scale with the memory cells, and may be uni-directional or bi-directional diodes. Biasing lines in the array allow biasing of selected and unselected select devices and segmentation elements with any desired bias, and may use biasing devices of the same construction as the segmentation elements.
    Type: Application
    Filed: December 15, 2014
    Publication date: April 16, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Aaron Yip