Abstract: Methods for programming sense flags may include programming memory cells coupled to first data lines in a main memory array, and programming memory cells coupled to second data lines in the main memory array while programming memory cells coupled to data lines in a flag memory array with flag data indicative of the memory cells coupled to the second data lines being programmed. Methods for sensing flags may include performing a sense operation on memory cells coupled to first data lines of a main memory array and memory cells coupled to data lines of a flag memory array, and determining a program indication of memory cells coupled to second data lines of the main memory array from the sense operation performed on the memory cells coupled to the data lines of the flag memory array.

Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.

Abstract: In a memory device, odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. Even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.

Abstract: Memories may include a first bi-directional select device connected between a first access line and a second access line, and a plurality of memory cells, each memory cell of the plurality of memory cells connected between the second access line and a respective third access line of a plurality of third access lines. Each memory cell of the plurality of memory cells comprises a respective second bi-directional select device, of a plurality of second bi-directional select devices, and a respective programmable element, of a plurality of programmable elements, connected in series.

Abstract: A flat scene modeler can more accurately simulate items in environments by receiving instructions to model a given 2D depiction of an item in a given 2D depiction of a room. The flat scene modeler can analyze the instructions and arrange a 3D model of the item in a 3D model of the room. Textures, materials, lighting, and virtual camera position are modified per the received instructions. Two-dimensional images rendered from the 3D models can be provided to a user as a simulation.

Abstract: Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string, and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.

Abstract: A flat scene modeler can more accurately simulate items in environments by receiving instructions to model a given 2D depiction of an item in a given 2D depiction of a room. The flat scene modeler can analyze the instructions and arrange a 3D model of the item in a 3D model of the room. Textures, materials, lighting, and virtual camera position are modified per the received instructions. Two-dimensional images rendered from the 3D models can be provided to a user as a simulation.

Abstract: An object can he simulated in an environment using a three-dimensional model of the object as viewed from a virtual camera at a position in the environment. The position in the environment can be determined using user input or through visual analysis of a video recording. Composite frames depicting the modeled object may be played back based on the orientation of the playback device.

Abstract: In one embodiment, an apparatus comprises a NAND flash memory device comprising a memory device controller and a memory NAND flash memory array, the NAND flash memory device to program data into a plurality of NAND flash memory cells coupled to a wordline in a single program sequence, wherein the plurality of NAND flash memory cells are coupled to a first plurality of bitlines and a second plurality of bitlines; couple the first plurality of bitlines to a fixed bias voltage in response to a first read command; apply a read voltage to the wordline coupled to the plurality of NAND flash memory cells; and sense, via the second plurality of bitlines, data stored in NAND flash memory cells coupled to the wordline, wherein at least some bitlines of the second plurality of bitlines are each in between and directly adjacent to two respective bitlines coupled to the fixed bias voltage.

Abstract: Memories may include a first select device connected between a first access line and a second access line, and a plurality of memory cells. Each memory cell of the plurality of memory cells may be connected between the second access line and a respective third access line of a plurality of third access lines. Each memory cell of the plurality of memory cells may include a respective second select device, of a plurality of second select devices, and a respective programmable element, of a plurality of programmable elements, connected in series, and the first select device and each second select device of the plurality of second select devices may each be formed of a same type of circuit element.

Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.

Abstract: An approach for simulating items in an environment, such as a room, is disclosed. A package file can store information including an image of the environment and metadata including an identifier that uniquely identifies a selected image. The package file can be used to regenerate a simulation of the item arranged over the image of the environment. Later changes can be made to the simulation of the item by accessing the metadata.

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

Abstract: Technology for performing read operations in a memory device or system is described. The device or system can include an array of memory cells. The device or system can include a first decode circuit, and can further include a second decode circuit. The device or system can include a voltage regulator configured to perform a read operation by providing, based on one or more signals received from at least one of the first decode circuit or the second decode circuit, a voltage to a selected plane or a selected sub-plane in the array of memory cells.

Abstract: Memories may include a first select device connected between a first access line and a second access line, and a plurality of memory cells. Each memory cell of the plurality of memory cells may be connected between the second access line and a respective third access line of a plurality of third access lines. Each memory cell of the plurality of memory cells may include a respective second select device, of a plurality of second select devices, and a respective programmable element, of a plurality of programmable elements, connected in series, and the first select device and each second select device of the plurality of second select devices may each be formed of a same type of circuit element.

Abstract: Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string, and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.

Abstract: An apparatus is described. The apparatus includes a three dimensional storage cell array structure. The apparatus also includes a staircase structure having alternating conductive and dielectric layers, wherein respective word lines are formed in the conductive layers. The word lines are connected to respective storage cells within the three dimensional storage cell array structure. The apparatus also includes upper word lines above the staircase structure that are connected to first vias that connect to respective steps of the staircase structure. The upper word lines are also connected to second vias that run vertically off a side of the staircase structure other than a side opposite the three dimensional storage cell array structure. The second vias are connected to respective word line driver transistors that are disposed beneath the staircase structure.

Abstract: Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

Abstract: Memory devices, memory arrays, and methods of operation of memory arrays with segmentation. Segmentation elements can scale with the memory cells, and may be uni-directional or bi-directional diodes. Biasing lines in the array allow biasing of selected and unselected select devices and segmentation elements with any desired bias, and may use biasing devices of the same construction as the segmentation elements.