Patents by Inventor Aaron Yip

Aaron Yip has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor devices including stair step structures, and related methods
    Patent number: 9165937
    Abstract: Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: October 20, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Aaron Yip, Qiang Tang, Chang Wan Ha
  • Sense operation flags in a memory device
    Patent number: 9135998
    Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: September 15, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • Methods and devices for memory reads with precharged data lines
    Patent number: 9099189
    Abstract: Methods of operating memory devices including precharging an adjacent pair of data lines to a particular voltage, isolating one data line of the adjacent pair of data lines from the particular voltage while maintaining the other data line of the adjacent pair of data lines at the particular voltage, and selectively discharging the one data line depending upon a data value of a selected memory cell of a string of memory cells associated with the one data line.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: August 4, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Erase operation control sequencing apparatus, systems, and methods
    Patent number: 9070459
    Abstract: Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: June 30, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Xiaojun Yu, Jin-man Han, Aaron Yip
  • SYSTEMS WITH MEMORY SEGMENTATION AND SYSTEMS WITH BIASING LINES TO RECEIVE SAME VOLTAGES DURING ACCESSING
    Publication number: 20150103578
    Abstract: Memory devices, memory arrays, and methods of operation of memory arrays with segmentation. Segmentation elements can scale with the memory cells, and may be uni-directional or bi-directional diodes. Biasing lines in the array allow biasing of selected and unselected select devices and segmentation elements with any desired bias, and may use biasing devices of the same construction as the segmentation elements.
    Type: Application
    Filed: December 15, 2014
    Publication date: April 16, 2015
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Aaron Yip
  • Sharing local control lines across multiple planes in a memory device
    Patent number: 8947934
    Abstract: Memory devices, methods for accessing a memory cell, and memory systems are disclosed. One such memory device includes a plurality of planes of memory cells. Each plane of memory cells includes series strings of memory cells that each have a select gate drain transistor. Control gates of corresponding select gates are coupled together by a shared local control line. Each of a plurality of global control lines are coupled to their corresponding local control line with only a single global select gate.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: February 3, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Diode segmentation in memory
    Patent number: 8929120
    Abstract: Memory devices, memory arrays, and methods of operation of memory arrays with segmentation. Segmentation elements can scale with the memory cells, and may be uni-directional or bi-directional diodes. Biasing lines in the array allow biasing of selected and unselected select devices and segmentation elements with any desired bias, and may use biasing devices of the same construction as the segmentation elements.
    Type: Grant
    Filed: August 29, 2012
    Date of Patent: January 6, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • SEMICONDUCTOR DEVICES INCLUDING STAIR STEP STRUCTURES, AND RELATED METHODS
    Publication number: 20150001613
    Abstract: Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed.
    Type: Application
    Filed: July 1, 2013
    Publication date: January 1, 2015
    Inventors: Aaron Yip, Qiang Tang, Chang Wan Ha
  • SINGLE CHECK MEMORY DEVICES AND METHODS
    Publication number: 20140351663
    Abstract: Memory devices and methods of operating memory devices are shown. Configurations described include circuits to perform a single check between programming pulses to determine a threshold voltage with respect to desired benchmark voltages. In one example, the benchmark voltages are used to change a programming speed of selected memory cells.
    Type: Application
    Filed: April 28, 2014
    Publication date: November 27, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Vishal Sarin, Aaron Yip, Tomoharu Tanaka
  • Select gate programming in a memory device
    Patent number: 8873297
    Abstract: Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source to unselected bit lines. Bit line-to-bit line capacitance, between the unselected bit lines and selected bit lines to be program inhibited, boosts the bit line voltage of the selected, inhibited bit lines to a target inhibit voltage. In one embodiment, the voltage on the selected, inhibited bit line can be increased in a plurality of inhibit steps whereby either one, two, or all of the steps can be used during the programming of unprogrammed select gates.
    Type: Grant
    Filed: September 5, 2013
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Shigekazu Yamada, Aaron Yip
  • THREE DIMENSIONAL MEMORY CONTROL CIRCUITRY
    Publication number: 20140146612
    Abstract: An integrated circuit includes a memory array, a wordline circuit, divided into at least two subcircuits, to control the memory array, and a bitline circuit, divided into at least two subcircuits, to control the memory array. The wordline subcircuits and the bitline subcircuits at least partially overlap separate respective regions of the memory array.
    Type: Application
    Filed: March 26, 2012
    Publication date: May 29, 2014
    Inventors: Mark Helm, Jung Sheng Hoei, Aaron Yip, Dzung Nguyen
  • Single check memory devices and methods
    Patent number: 8711616
    Abstract: Memory devices and methods of operating memory devices are shown. Configurations described include circuits to perform a single check between programming pulses to determine a threshold voltage with respect to desired benchmark voltages. In one example, the benchmark voltages are used to change a programming speed of selected memory cells.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: April 29, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Vishal Sarin, Aaron Yip, Tomoharu Tanaka
  • REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES
    Publication number: 20140098606
    Abstract: Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then be applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.
    Type: Application
    Filed: October 8, 2012
    Publication date: April 10, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Aaron Yip
  • DIODE SEGMENTATION IN MEMORY
    Publication number: 20140063892
    Abstract: Memory devices, memory arrays, and methods of operation of memory arrays with segmentation. Segmentation elements can scale with the memory cells, and may be uni-directional or bi-directional diodes. Biasing lines in the array allow biasing of selected and unselected select devices and segmentation elements with any desired bias, and may use biasing devices of the same construction as the segmentation elements.
    Type: Application
    Filed: August 29, 2012
    Publication date: March 6, 2014
    Inventor: Aaron Yip
  • METHODS AND DEVICES FOR MEMORY READS WITH PRECHARGED DATA LINES
    Publication number: 20140029353
    Abstract: Methods of operating memory devices including precharging an adjacent pair of data lines to a particular voltage, isolating one data line of the adjacent pair of data lines from the particular voltage while maintaining the other data line of the adjacent pair of data lines at the particular voltage, and selectively discharging the one data line depending upon a data value of a selected memory cell of a string of memory cells associated with the one data line.
    Type: Application
    Filed: September 27, 2013
    Publication date: January 30, 2014
    Applicant: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Access line management in a memory device
    Patent number: 8638632
    Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.
    Type: Grant
    Filed: September 23, 2010
    Date of Patent: January 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Benjamin Louie, Ali Mohammadzadeh, Aaron Yip
  • SELECT GATE PROGRAMMING IN A MEMORY DEVICE
    Publication number: 20140003151
    Abstract: Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source to unselected bit lines. Bit line-to-bit line capacitance, between the unselected bit lines and selected bit lines to be program inhibited, boosts the bit line voltage of the selected, inhibited bit lines to a target inhibit voltage. In one embodiment, the voltage on the selected, inhibited bit line can be increased in a plurality of inhibit steps whereby either one, two, or all of the steps can be used during the programming of unprogrammed select gates.
    Type: Application
    Filed: September 5, 2013
    Publication date: January 2, 2014
    Applicant: Micron Technology, Inc.
    Inventors: Shigekazu Yamada, Aaron Yip
  • Methods and devices for memory reads with precharged data lines
    Patent number: 8547750
    Abstract: Methods and devices for memory reads involving precharging adjacent data lines to a particular voltage for a read operation. During the operation, a data line associated with a selected memory cell is selectively discharged from the particular voltage depending upon the data value of the selected memory cell while the adjacent data line is maintained at the particular voltage. Various embodiments include the array architecture to facilitate precharging the adjacent pair of data lines to a particular voltage and maintaining the unselected data line at the particular voltage during a sensing phase of a read operation.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: October 1, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Multi-pass programming in a memory device
    Patent number: 8547749
    Abstract: A method for programming a memory device, a memory device, and a memory system are provided. According to at least one such method, a first programming pass generates a plurality of first programming pulses to increase the threshold voltages of target memory cells to either a pre-program level or to the highest programmed threshold. A second programming pass applies a plurality of second programming pulses to the target memory cells to increase their threshold voltages only if they were programmed to the pre-program level. The target memory cells programmed to their respective target threshold levels during the first pass are not programmed further.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: October 1, 2013
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Select gate programming in a memory device
    Patent number: 8542534
    Abstract: Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source line to unselected bit lines. Bit line-to-bit line capacitance, between the unselected bit lines and selected bit lines to be program inhibited, boosts the bit line voltage of the selected, inhibited bit lines to a target inhibit voltage. In one embodiment, the voltage on the selected, inhibited bit line can be increased in a plurality of inhibit steps whereby either one, two, or all of the steps can be used during the programming of unprogrammed select gates.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: September 24, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Shigekazu Yamada, Aaron Yip