Patents by Inventor Aaron Yip

Aaron Yip has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110158003
    Abstract: An embodiment of a method of erasing a target memory cell includes grounding a selected word line commonly coupled to portions of a row of memory cells respectively formed on first well regions of a plurality of first well regions of a first conductivity type formed in a second well region of a second conductivity type, the at least one target memory cell coupled to the selected word line and formed on one of the first well regions, the first well regions electrically isolated from each other; applying a first voltage to the first well region on which the at least one target memory cell is formed; and applying a second voltage to unselected word lines, each unselected word line commonly coupled to portions of a row of memory cells not targeted for erasing and respectively formed on the first well regions.
    Type: Application
    Filed: March 4, 2011
    Publication date: June 30, 2011
    Inventor: Aaron Yip
  • Patent number: 7957198
    Abstract: In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, the p-well is biased with the negative voltage and the erase verify operation is performed to determine the erased state of the cell(s).
    Type: Grant
    Filed: April 19, 2010
    Date of Patent: June 7, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Patent number: 7924617
    Abstract: Non-volatile memory devices for providing selective compaction verification and/or selective compaction to facilitate a tightening of the distribution of threshold voltages in memory devices utilizing a NAND architecture. By providing for compaction verification and/or compaction on less than all word lines of a NAND string, increased tightening of the distribution may be achieved over prior methods performed concurrently on all word lines of a NAND string.
    Type: Grant
    Filed: August 25, 2009
    Date of Patent: April 12, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Patent number: 7903464
    Abstract: An embodiment of a method includes applying a first voltage to a selected word line commonly coupled to portions of a row of memory cells respectively formed on first well regions of a plurality of first well regions of a first conductivity type formed in a second well region of a second conductivity type, at least one target memory cell coupled to the selected word line and formed on one of the first well regions, the first well regions electrically isolated from each other; applying a second voltage to unselected word lines, each unselected word line commonly coupled to portions of a row of memory cells not targeted for programming and respectively formed on the first well regions; and applying a third voltage to those first well regions that do not include the at least one target memory cell.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: March 8, 2011
    Assignee: Micron Technologies, Inc.
    Inventor: Aaron Yip
  • Patent number: 7882306
    Abstract: A memory device capable of sequentially outputting multiple pages of cached data while mitigating any interruption typically caused by fetching and transferring operations. The memory device outputs cached data from a first page while data from a second page is fetched into sense amplifier circuitry. When the outputting of the first page reaches a predetermined transfer point, a portion of the fetched data from the second page is transferred into the cache at the same time the remainder of the cached first page is being output. The remainder of the second page is transferred into the cache after all of the data from the first page is output while the outputting of the first portion of the second page begins with little or no interruption.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: February 1, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Publication number: 20110019474
    Abstract: Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches.
    Type: Application
    Filed: October 5, 2010
    Publication date: January 27, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Jin-Man Han, Aaron Yip
  • Publication number: 20110007562
    Abstract: The present invention discloses a method of programming an MLC NAND flash memory device comprising: selecting a start value for a program voltage for a lower page; incrementing said program voltage to program said lower page; verifying a threshold voltage; determining said program voltage to achieve a desired value for said threshold voltage; applying an offset to said program voltage; and obtaining a start value for said program voltage for an upper page.
    Type: Application
    Filed: July 13, 2009
    Publication date: January 13, 2011
    Inventor: Aaron Yip
  • Publication number: 20100302844
    Abstract: A flash memory architecture that provides a mechanism for reducing floating gate to floating gate coupling. The floating gates of the memory cells are shifted, either vertically or horizontally thereby offsetting the floating gates of the memory cells to an intervening space between the gates of adjacent memory cells. The shift of the floating gates decreases the floating gate to floating gate coupling.
    Type: Application
    Filed: June 18, 2010
    Publication date: December 2, 2010
    Inventors: Hagop A. Nazarian, Aaron Yip
  • Publication number: 20100296348
    Abstract: Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.
    Type: Application
    Filed: July 30, 2010
    Publication date: November 25, 2010
    Inventors: Xiaojun Yu, Jin-man Han, Aaron Yip
  • Patent number: 7821830
    Abstract: Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: October 26, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Jin-Man Han, Aaron Yip
  • Patent number: 7778086
    Abstract: Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.
    Type: Grant
    Filed: January 25, 2007
    Date of Patent: August 17, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Xiaojun Yu, Jin-man Han, Aaron Yip
  • Publication number: 20100202214
    Abstract: In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, the p-well is biased with the negative voltage and the erase verify operation is performed to determine the erased state of the cell(s).
    Type: Application
    Filed: April 19, 2010
    Publication date: August 12, 2010
    Inventor: Aaron Yip
  • Patent number: 7773412
    Abstract: A flash memory architecture that provides a mechanism for reducing floating gate to floating gate coupling. The floating gates of the memory cells are shifted, either vertically or horizontally thereby offsetting the floating gates of the memory cells to an intervening space between the gates of adjacent memory cells. The shift of the floating gates decreases the floating gate to floating gate coupling.
    Type: Grant
    Filed: May 22, 2006
    Date of Patent: August 10, 2010
    Inventors: Hagop A. Nazarian, Aaron Yip
  • Publication number: 20100142280
    Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.
    Type: Application
    Filed: February 11, 2010
    Publication date: June 10, 2010
    Inventors: Dzung H. Nguyen, Benjamin Louie, Hagop A. Nazarian, Aaron Yip, Jin-Man Han
  • Publication number: 20100128523
    Abstract: A method for programming a memory device, a memory device, and a memory system are provided. According to at least one such method, a first programming pass generates a plurality of first programming pulses to increase the threshold voltages of target memory cells to either a pre-program level or to the highest programmed threshold. A second programming pass applies a plurality of second programming pulses to the target memory cells to increase their threshold voltages only if they were programmed to the pre-program level. The target memory cells programmed to their respective target threshold levels during the first pass are not programmed further.
    Type: Application
    Filed: November 21, 2008
    Publication date: May 27, 2010
    Inventor: Aaron Yip
  • Patent number: 7710760
    Abstract: A method and apparatus for charging large capacitances of a circuit, such as an integrated circuit, without imparting noise on an operating voltage. A comparator compares a reference voltage to a voltage representing the voltage on the capacitance and a multiplexer routes one of an external voltage or an operating voltage derived from said external voltage to charge the capacitance depending on the output of the comparator.
    Type: Grant
    Filed: May 8, 2008
    Date of Patent: May 4, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Patent number: 7707368
    Abstract: Methods and apparatus are provided. A memory device has a memory array, base trim circuitry adapted to store base control parameter values common to the memory array, and a reference trim circuit corresponding to a portion of the memory array. The reference trim circuit is adapted to store one or more reference control parameter values for respectively correcting one or more of the base control parameter values of the base trim circuitry for application to the portion of the memory array. The memory device may include an index circuit corresponding to the reference trim circuit. The index circuit is adapted to store one or more index parameter values for respectively selecting the one or more base control parameter values of the base trim circuitry for correction by the one or more reference control parameter values of the reference trim circuit.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: April 27, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Benjamin Louie, Aaron Yip, Jin-Man Han
  • Patent number: 7701741
    Abstract: In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, the p-well is biased with the negative voltage and the erase verify operation is performed to determine the erased state of the cell(s).
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: April 20, 2010
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Patent number: 7688630
    Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: March 30, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Dzung H. Nguyen, Benjamin Louie, Hagop A. Nazarian, Aaron Yip, Jin-Man Han
  • Publication number: 20100061155
    Abstract: An embodiment of a method includes applying a first voltage to a selected word line commonly coupled to portions of a row of memory cells respectively formed on first well regions of a plurality of first well regions of a first conductivity type formed in a second well region of a second conductivity type, at least one target memory cell coupled to the selected word line and formed on one of the first well regions, the first well regions electrically isolated from each other; applying a second voltage to unselected word lines, each unselected word line commonly coupled to portions of a row of memory cells not targeted for programming and respectively formed on the first well regions; and applying a third voltage to those first well regions that do not include the at least one target memory cell.
    Type: Application
    Filed: November 9, 2009
    Publication date: March 11, 2010
    Inventor: Aaron Yip