Patents by Inventor Aaron Yip

Aaron Yip has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS AND DEVICES FOR MEMORY READS WITH PRECHARGED DATA LINES
    Publication number: 20120257450
    Abstract: Methods and devices for memory reads involving precharging adjacent data lines to a particular voltage for a read operation. During the operation, a data line associated with a selected memory cell is selectively discharged from the particular voltage depending upon the data value of the selected memory cell while the adjacent data line is maintained at the particular voltage.
    Type: Application
    Filed: April 7, 2011
    Publication date: October 11, 2012
    Inventor: Aaron Yip
  • Erase operation control sequencing apparatus, systems, and methods
    Patent number: 8259508
    Abstract: Apparatus, systems, and methods may operate to receive an external erase command at a control circuit coupled to an erasable memory array located on a substrate. A global select gate voltage may thereafter be enabled for application to wordline transistors coupled to the erasable memory array after a voltage applied to the substrate has reached a preselected initiation voltage level between about zero volts and an ultimate erase voltage.
    Type: Grant
    Filed: July 30, 2010
    Date of Patent: September 4, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Xiaojun Yu, Jin-man Han, Aaron Yip
  • PROGRAMMING MEMORY DEVICES
    Publication number: 20120221779
    Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.
    Type: Application
    Filed: May 4, 2012
    Publication date: August 30, 2012
    Applicant: ROUND ROCK RESEARCH, LLC
    Inventors: Dzung H. Nguyen, Benjamin Louie, Hagop A. Nazarian, Aaron Yip, Jin-Man Han
  • SINGLE CHECK MEMORY DEVICES AND METHODS
    Publication number: 20120163076
    Abstract: Memory devices and methods of operating memory devices are shown. Configurations described include circuits to perform a single check between programming pulses to determine a threshold voltage with respect to desired benchmark voltages. In one example, the benchmark voltages are used to change a programming speed of selected memory cells.
    Type: Application
    Filed: December 22, 2010
    Publication date: June 28, 2012
    Inventors: Vishal Sarin, Aaron Yip, Tomoharu Tanaka
  • Memory devices and methods of their operation including selective compaction verify operations
    Patent number: 8184481
    Abstract: Memory devices and methods of their operation, where following an erasure of a string of memory cells, a selective compaction verify operation is performed on one or more, but less than all, of the memory cells of the string, and, if the selective compaction verify operation indicates compaction is desired, a soft programming pulse is applied to one or more of the memory cells of the string.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: May 22, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • SENSE OPERATION FLAGS IN A MEMORY DEVICE
    Publication number: 20120117306
    Abstract: Memory devices, methods for programming sense flags, methods for sensing flags, and memory systems are disclosed. In one such memory device, the odd bit lines of a flag memory cell array are connected with a short circuit to a dynamic data cache. The even bit lines of the flag memory cell array are disconnected from the dynamic data cache. When an even page of a main memory cell array is read, the odd flag memory cells, comprising flag data, are read at the same time so that it can be determined whether the odd page of the main memory cell array has been programmed. If the flag data indicates that the odd page has not been programmed, threshold voltage windows can be adjusted to determine the states of the sensed even memory cell page.
    Type: Application
    Filed: November 9, 2010
    Publication date: May 10, 2012
    Inventors: Shafqat Ahmed, Khaled Hasnat, Pranav Kalavade, Krishna Parat, Aaron Yip, Mark A. Helm, Andrew Bicksler
  • Programming memory devices
    Patent number: 8174889
    Abstract: A target memory cell of a memory device is programmed by applying a programming voltage to a word line that includes the target memory cell, determining whether the target memory cell is programmed, and increasing the programming voltage by a step voltage if it is determined that the target memory cell is not programmed. An initial programming voltage and the step voltage are each selectable after fabrication of the memory device.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: May 8, 2012
    Assignee: Round Rock Research, LLC
    Inventors: Dzung H. Nguyen, Benjamin Louie, Hagop A. Nazarian, Aaron Yip, Jin-Man Han
  • Method and apparatus for providing a non-volatile memory with reduced cell capacitive coupling
    Patent number: 8164951
    Abstract: A flash memory architecture that provides a mechanism for reducing floating gate to floating gate coupling. The floating gates of the memory cells are shifted, either vertically or horizontally thereby offsetting the floating gates of the memory cells to an intervening space between the gates of adjacent memory cells. The shift of the floating gates decreases the floating gate to floating gate coupling.
    Type: Grant
    Filed: June 18, 2010
    Date of Patent: April 24, 2012
    Assignee: Micron Technology, Inc.
    Inventors: Hagop A. Nazarian, Aaron Yip
  • ACCESS LINE MANAGEMENT IN A MEMORY DEVICE
    Publication number: 20120075934
    Abstract: Memory devices and methods are disclosed, such as devices configured to store a number of access line biasing patterns to be applied during a memory device operation performed on a particular row of memory cells in the memory device. Memory devices are further configured to support modification of the stored bias patterns, providing flexibility in biasing access lines through changes to the bias patterns stored in the memory device. Methods and devices further facilitate performing memory device operations under multiple biasing conditions to evaluate and characterize the memory device by adjustment of the stored bias patterns without requiring an associated hardware change to the memory device.
    Type: Application
    Filed: September 23, 2010
    Publication date: March 29, 2012
    Inventors: Benjamin Louie, Ali Mohammadzadeh, Aaron Yip
  • MEMORY WITH INTERLEAVED READ AND REDUNDANT COLUMNS
    Publication number: 20120069659
    Abstract: Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches.
    Type: Application
    Filed: November 30, 2011
    Publication date: March 22, 2012
    Applicant: Micron Technology, Inc.
    Inventors: Jin-Man Han, Aaron Yip
  • Verifying an erase threshold in a memory device
    Patent number: 8125836
    Abstract: In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, the p-well is biased with the negative voltage and the erase verify operation is performed to determine the erased state of the cell(s).
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: February 28, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • MULTI-PASS PROGRAMMING IN A MEMORY DEVICE
    Publication number: 20120044769
    Abstract: A method for programming a memory device, a memory device, and a memory system are provided. According to at least one such method, a first programming pass generates a plurality of first programming pulses to increase the threshold voltages of target memory cells to either a pre-program level or to the highest programmed threshold. A second programming pass applies a plurality of second programming pulses to the target memory cells to increase their threshold voltages only if they were programmed to the pre-program level. The target memory cells programmed to their respective target threshold levels during the first pass are not programmed further.
    Type: Application
    Filed: November 1, 2011
    Publication date: February 23, 2012
    Inventor: Aaron YIP
  • Method of erasing memory cell
    Patent number: 8116143
    Abstract: An embodiment of a method of erasing a target memory cell includes grounding a selected word line commonly coupled to portions of a row of memory cells respectively formed on first well regions of a plurality of first well regions of a first conductivity type formed in a second well region of a second conductivity type, the at least one target memory cell coupled to the selected word line and formed on one of the first well regions, the first well regions electrically isolated from each other; applying a first voltage to the first well region on which the at least one target memory cell is formed; and applying a second voltage to unselected word lines, each unselected word line commonly coupled to portions of a row of memory cells not targeted for erasing and respectively formed on the first well regions.
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: February 14, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • Dynamic wordline start voltage for nand programming
    Patent number: 8111549
    Abstract: The present invention discloses a method of programming an MLC NAND flash memory device comprising: selecting a start value for a program voltage for a lower page; incrementing said program voltage to program said lower page; verifying a threshold voltage; determining said program voltage to achieve a desired value for said threshold voltage; applying an offset to said program voltage; and obtaining a start value for said program voltage for an upper page.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: February 7, 2012
    Assignee: Intel Corporation
    Inventor: Aaron Yip
  • Flash memory device with redundant columns
    Patent number: 8081511
    Abstract: Apparatus and methods are disclosed, such as those involving a flash memory device. One such apparatus includes a memory block including a plurality of columns. Each of the columns includes a bit line and a plurality of memory cells on the bit line. The plurality of columns include a plurality of groups of regular columns and a plurality of groups of redundant columns. The apparatus also includes a plurality of data latches. Each of the data latches is configured to store data read from a respective one group of regular columns. The apparatus further includes a plurality of redundant data latches. Each of the redundant data latches is configured to store data read from a respective one group of redundant columns. The apparatus also includes a multiplexer configured to selectively output data from the plurality of data latches and the plurality of redundant data latches.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: December 20, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Jin-Man Han, Aaron Yip
  • Memory block reallocation in a flash memory device
    Patent number: 8072816
    Abstract: A non-volatile memory device has the pages of a certain memory block reallocated to other blocks in order to increase decrease disturb and increase reliability. Each of the reallocation blocks that contain the reallocated pages from the desired memory block are coupled to a wordline driver. These wordline drivers have a subset of the global wordlines as inputs. The desired wordline driver is selected by an appropriate select signal from a block decoder and an indication on an appropriate global wordline. This causes the wordline driver to generate a local wordline to the desired block with the reallocated page to be accessed.
    Type: Grant
    Filed: June 5, 2009
    Date of Patent: December 6, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Jin-Man Han, Aaron Yip
  • Multi-pass programming in a memory device
    Patent number: 8064252
    Abstract: A method for programming a memory device, a memory device, and a memory system are provided. According to at least one such method, a first programming pass generates a plurality of first programming pulses to increase the threshold voltages of target memory cells to either a pre-program level or to the highest programmed threshold. A second programming pass applies a plurality of second programming pulses to the target memory cells to increase their threshold voltages only if they were programmed to the pre-program level. The target memory cells programmed to their respective target threshold levels during the first pass are not programmed further.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: November 22, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Aaron Yip
  • SELECT GATE PROGRAMMING IN A MEMORY DEVICE
    Publication number: 20110249503
    Abstract: Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source line to unselected bit lines. Bit line-to-bit line capacitance, between the unselected bit lines and selected bit lines to be program inhibited, boosts the bit line voltage of the selected, inhibited bit lines to a target inhibit voltage. In one embodiment, the voltage on the selected, inhibited bit line can be increased in a plurality of inhibit steps whereby either one, two, or all of the steps can be used during the programming of unprogrammed select gates.
    Type: Application
    Filed: April 8, 2010
    Publication date: October 13, 2011
    Inventors: Shigekazu Yamada, Aaron Yip
  • VERIFYING AN ERASE THRESHOLD IN A MEMORY DEVICE
    Publication number: 20110235433
    Abstract: In one or more embodiments, a memory device is disclosed as having an erase verify operation that includes a negative bias on the p-well in which the memory cell or cells being erased are formed. After an erase pulse is applied to the selected cells to be erased, the p-well is biased with the negative voltage and the erase verify operation is performed to determine the erased state of the cell(s).
    Type: Application
    Filed: June 6, 2011
    Publication date: September 29, 2011
    Inventor: Aaron Yip
  • MEMORY DEVICES AND METHODS OF THEIR OPERATION INCLUDING SELECTIVE COMPACTION VERIFY OPERATIONS
    Publication number: 20110188320
    Abstract: Memory devices and methods of their operation, where following an erasure of a string of memory cells, a selective compaction verify operation is performed on one or more, but less than all, of the memory cells of the string, and, if the selective compaction verify operation indicates compaction is desired, a soft programming pulse is applied to one or more of the memory cells of the string.
    Type: Application
    Filed: April 11, 2011
    Publication date: August 4, 2011
    Inventor: Aaron Yip