Patents by Inventor ADARSH

ADARSH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250099014
    Abstract: The embodiments of the present disclosure herein address unresolved problems of quality of signals in real time for wearables to provide optimal signals which can be used for brain signal based applications. Further, conventional techniques fail to provide real-time calibration of wearable devices, to understand the quality of the signals from the wearable device. Embodiments herein provide a method and system for a real-time calibration of one or more Electroencephalography (EEG) signals received from a wearable Ear-EEG device. The system is leveraging quality of signals in real time for wearables to provide optimal signals which can be used for early detection of neurodegenerative disease and brain-computer interface (BCI) applications. Further, the system is able to detect electrodes in the wearable device where the EEG signals have not been collected because the contact was not established.
    Type: Application
    Filed: September 3, 2024
    Publication date: March 27, 2025
    Applicant: Tata Consultancy Services Limited
    Inventors: Jayavardhana Rama GUBBI LAKSHMINARASIMHA, Tanuja JAYAS, Kartik MURALIDHARAN, Adarsh ANAND, Ramesh Kumar RAMAKRISHNAN, Arpan PAL
  • Patent number: 12261080
    Abstract: A method of forming a structure includes forming an alternating stack of first material layers and second material layers over a substrate, forming a mask layer over the alternating stack, forming a cavity in the mask layer, forming a first cladding liner on a sidewall of the cavity in the mask layer, and forming a via opening the alternating stack by performing an anisotropic etch process that transfers a pattern of the cavity in the mask layer through the alternating stack using a combination of the first cladding liner and the mask layer as an etch mask.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: March 25, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Roshan Jayakhar Tirukkonda, Monica Titus, Senaka Kanakamedala, Raghuveer S. Makala, Rahul Sharangpani, Adarsh Rajashekhar
  • Publication number: 20250093234
    Abstract: A crack detection system for a cylinder head associated with an internal combustion engine of a locomotive is disclosed. The crack detection system comprises: a closed-loop coolant system for cooling the cylinder head; a sensor assembly including a pressure sensor, and a speed sensor; and a controller in communication with the sensor assembly. The controller is configured to monitor a coolant pressure feedback and an engine duty cycle of the internal combustion engine. The controller is further configured to communicate an alert signal indicative of an existence of a crack in the cylinder head when: coolant pressure signals are greater than or equal to a first threshold and less than a second threshold; a pressure decay is calculated greater than a third threshold.
    Type: Application
    Filed: September 14, 2023
    Publication date: March 20, 2025
    Applicant: Progress Rail Lomotive Inc.
    Inventors: Adarsh G. NAIR, Raji REXAVIER
  • Publication number: 20250093942
    Abstract: Power sources provide power in a range with a maximum supply voltage provided under zero-load current conditions. Power circuits in an IC receive and aggregate indications of load current from processor circuits in processor circuit clusters and, reduce power consumption in the IC during zero or low load current conditions by generating a voltage control signal to reduce the supply voltage. Reducing the no-load voltage also reduces stress on gate oxides of transistors in the IC to increase oxide longevity. Based on the aggregated load current indications, which is periodically updated, the no-load supply voltage may be incrementally reduced down to a voltage threshold over the course of multiple periods. In some examples, the power circuits receive throttle signals when the processor circuits are throttled due to a voltage droop, and such signals may cause the power circuits to generate a control signal to increase the no-load voltage.
    Type: Application
    Filed: September 19, 2023
    Publication date: March 20, 2025
    Inventors: Mahadevamurty Nemani, Adarsh Baraka Ravi, Nitin Makhija, Pradeep Kanapathipillai
  • Publication number: 20250093931
    Abstract: Autonomously managing core cluster frequencies using performance statistics in processor devices is disclosed herein. In some aspects, a cluster power management circuit of a processor device collects Activity Management Unit (AMU) statistics for multiple processor cores for each of one or more frequency operating points over a time interval. Based on the AMU statistics, the cluster power management circuit generates a performance model representing processor performance as a function of frequency, and uses the performance model and a power consumption measurement to generate an energy-per-instruction (EI) model representing energy per instruction as a function of frequency. The cluster power management circuit then generates an advantage model based on a first rate of change of the performance model as a function of frequency and a second rate of change of the EI model as a function of frequency, and identifies a target frequency operating point based on the advantage model.
    Type: Application
    Filed: September 15, 2023
    Publication date: March 20, 2025
    Inventors: Mahadevamurty Nemani, Anubhav Mishra, Arun Sukheja, Nitin Makhija, Adarsh Baraka Ravi
  • Patent number: 12256096
    Abstract: A device to code a point cloud data that includes a memory configured to store data representing points of a point cloud, and one or more processors implemented in circuitry and configured to: determine height values of points in a point cloud; code a data structure including data that represents a top threshold and a bottom threshold; classify points having height values between the top threshold and the bottom threshold into the set of ground points; classify points having height values above the top threshold or below the bottom threshold into the set of object points. The one or more processors code the ground points and the object points according to the classifications. The one or more processors code a geometry data unit header that includes data that overrides or refines the data of the data structure for the at least one of the top threshold or the bottom threshold.
    Type: Grant
    Filed: April 1, 2024
    Date of Patent: March 18, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Luong Pham Van, Adarsh Krishnan Ramasubramonian, Bappaditya Ray, Geert Van der Auwera, Marta Karczewicz
  • Patent number: 12255242
    Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel, a memory film in contact with the vertical semiconductor channel, and a vertical stack of tubular dielectric spacers laterally surrounding the memory film. The tubular dielectric spacers may include tubular graded silicon oxynitride portions having a composition gradient such that an atomic concentration of nitrogen decreases with a lateral distance from an outer sidewall of the memory film, or may include tubular composite dielectric spacers including a respective tubular silicon oxide spacer and a respective tubular dielectric metal oxide spacer. Each of the electrically conductive layers has a hammerhead-shaped vertical cross-sectional profile.
    Type: Grant
    Filed: January 28, 2022
    Date of Patent: March 18, 2025
    Assignee: Sandisk Technologies Inc.
    Inventors: Adarsh Rajashekhar, Raghuveer S. Makala, Koichi Matsuno
  • Patent number: 12248064
    Abstract: Smart glasses including a first audio device, a second audio device, a frame including a first portion, a second portion, and a third portion, the second portion and the third portion are moveable in relation to the first portion, the second portion including the first audio device and the third portion including the second audio device, and a processor configured to cause the first audio device to generate a signal, receive the signal via the second audio device, estimate a distance based on the received signal, and determine a configuration of the frame.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: March 11, 2025
    Assignee: GOOGLE LLC
    Inventors: Dongeek Shin, Adarsh Prakash Murthy Kowdle, Jingying Hu, Andrea Colaco
  • Publication number: 20250077212
    Abstract: A system includes a computing hardware system, a network storage, and one or more data sources. A local processor of a data collector node associated with each data source is configured to collect and store incremental application data to the network storage and transmit a file path of the application data to a data API of the computing hardware system. A processor of the computing hardware system is configured to access the received file path and load the application data into a local memory. The processor is configured to generate a compute thread comprising compute queue and data queue and associate the compute thread to the host application. The processor updates the incremental application data from the local memory to the GPU memory through the compute thread and subsequently to local storage. In addition, the processor updates the application data without restarting the host application.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 6, 2025
    Applicant: Innoplexus AG
    Inventor: Adarsh Jain
  • Publication number: 20250078081
    Abstract: A method for identifying fraudulent cryptographic currency transactions using a deep neural network includes: receiving, by a receiver of a processing server, a source dataset, the source dataset including labeled source data associated with a plurality of source features and being associated with a source domain; receiving, by the receiver of the processing server, a target dataset, the target dataset including unlabeled target data associated with a plurality of target features and being associated with a target domain; combining, by a processor of the processing server, at least a subset of the plurality of source features and at least a subset of the plurality of target features into a combined data layer; training, by the processor of the processing server, a deep neural network using a domain adaptation algorithm and the combined data layer to identify a set of final features.
    Type: Application
    Filed: September 5, 2023
    Publication date: March 6, 2025
    Applicant: Mastercard International Incorporated
    Inventors: Soumyadeep GHOSH, Adarsh PATANKAR, Rohit JAIN, Deepak YADAV
  • Patent number: 12244805
    Abstract: Techniques are described for decoding video data. A video decoder may determine chroma blocks in a chroma quantization group (QG) of the video data, determine a quantization parameter predictor that is the same for each of the chroma blocks of the chroma QG, determine an offset value that is the same for two or more of the chroma blocks of the chroma QG, determine a quantization parameter value for each of the two or more of the chroma blocks in the chroma QG based on the quantization parameter predictor and the offset value inverse quantize coefficients of one or more residual blocks for the chroma blocks based on the determined quantization parameter value, generate the one or more residual blocks based on the inverse quantized coefficients, and reconstruct the chroma blocks based on the one or more residual blocks.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: March 4, 2025
    Assignee: QUALCOMM Incorporated
    Inventors: Adarsh Krishnan Ramasubramonian, Geert Van der Auwera, Wei-Jung Chien, Han Huang, Yu Han, Bappaditya Ray, Marta Karczewicz
  • Patent number: 12243776
    Abstract: A source-level semiconductor layer and an alternating stack of first material layers and second material layers is formed above a substrate. A hard mask layer is formed over the alternating stack, and is subsequently patterned to provide a pattern of cavities therethrough. Via openings are formed through the alternating stack by performing an anisotropic etch process. A cladding liner is formed on sidewalls of the cavities in the hard mask layer and on a top surface of the hard mask layer. The via openings are vertically extended at least through the source-level semiconductor layer by performing a second anisotropic etch process employing a combination of the cladding liner and the hard mask layer as an etch mask.
    Type: Grant
    Filed: October 22, 2021
    Date of Patent: March 4, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Roshan Jayakhar Tirukkonda, Senaka Kanakamedala, Raghuveer S. Makala, Rahul Sharangpani, Monica Titus, Adarsh Rajashekhar
  • Patent number: 12236112
    Abstract: A method for securing a data storage device (DSD) against rogue behaviour by a host, the method executed by a controller of the DSD and comprising: determining a host type of the host; detecting one or more access activities performed by the host on the DSD; processing the one or more access activities to determine a security threat level of the host, wherein the security threat level is determined by weighting one or more corresponding access activity parameters by one or more impact weights; and in response to determining that the security threat level of the host is greater than or equal to a rogue host threat level, controlling the access activities performable by the host on the DSD to safeguard the DSD against the host, wherein the one or more impact weights are dynamically determined based on the host type.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: February 25, 2025
    Assignee: Sandisk Technologies, Inc.
    Inventors: Ramanathan Muthiah, Adarsh Sreedhar, Niraj Srimal
  • Publication number: 20250058767
    Abstract: A method is for determining a maximum coefficient of friction of a wheel of a vehicle on a road. The method includes: determining a reference wheel acceleration of the wheel, wherein accelerations and a yaw behavior of the wheel and/or of the vehicle on the road are determined, determining a real wheel acceleration of the wheel, wherein a slip behavior of the wheel on the road is determined, comparing the reference wheel acceleration and the real wheel acceleration, in particular forming a quotient, determining the maximum coefficient of friction from the comparison of the reference wheel acceleration and the real wheel acceleration.
    Type: Application
    Filed: November 5, 2024
    Publication date: February 20, 2025
    Inventor: Adarsh Venkata Padmanabhan
  • Patent number: 12229284
    Abstract: Disclosed are various embodiments of a multiuser unified endpoint management (UEM) system. A device check-in can be received from a client device. The device check-in can include a device identifier that uniquely identifies the client device with respect to other client devices and a user identifier that uniquely identifies the user of the client device with respect to other users of the client device. In response, a device channel identifier associated with the device identifier and a user channel identifier associated with both the user identifier and the device identifier can be obtained. Then a first set of entitlements associated with the device channel identifier and a second set of entitlements associated with the user channel identifier can be selected. Both sets of entitlements can be provided to the client device in response to the device check-in.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: February 18, 2025
    Assignee: Omnissa, LLC
    Inventors: Senthil Parthasarathy, Kevin B. Sheehan, Muhammad Anadil Furqan, Haroon Barlas, Amruta Moghe, Kishore Krishnakumar, Adarsh Subhash Chandra Jain
  • Publication number: 20250048061
    Abstract: In some implementations, a device may retrieve, from a user database, information identifying a plurality of users that are to be subjected to an adverse action. The device may retrieve, from an event stream, event data relating to an incident that has affected an affected area, where the event data indicates at least a location of the affected area. The device may identify, based on the information identifying the plurality of users, one or more users of the plurality of users that reside in the location of the affected area. The device may cause transmission of communications relating to the adverse action for each of the plurality of users, except for the one or more users that reside in the location of the affected area.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Inventors: Jason Andrew LINENBERGER, Haresh Devrajbhai DIYORA, Thiru GUNTURU, Adarsh TANDON, Sabrina PENG, Leland DRIVER, Angelique BAUTISTA, Lindsey SANTOLA, Daniel PEREIRA
  • Publication number: 20250045761
    Abstract: Methods, systems, and media for screening users of a virtual environment are provided.
    Type: Application
    Filed: March 15, 2024
    Publication date: February 6, 2025
    Inventors: Tanishq Nimale, Prashant Jawale, Abhishek Vyas, Adarsh Singh, Vinay Gaykar
  • Patent number: 12219776
    Abstract: A semiconductor structure includes an active region including a source region, a drain region, and a channel region extending between the source region and the drain region, a gate stack, and a gate dielectric layer located between the gate stack and the active region. The gate stack includes an electrically conductive gate electrode and a single crystalline III-nitride ferroelectric plate located between the electrically conductive gate electrode and the gate dielectric layer, and an entirety of the single crystalline III-nitride ferroelectric plate is single crystalline.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: February 4, 2025
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Adarsh Rajashekhar, Raghuveer S. Makala, Kartik Sondhi
  • Patent number: 12197318
    Abstract: Aspects of a storage device including a memory and a controller are provided. The controller may collect, by an association rule mining (ARM) model, file system data from a host file system, the file system data defining at least one attribute of a file. The controller may receive, from the host, a memory command associated with the file. The controller can associate, by the ARM model, the at least one attribute with the file. The controller may perform the memory command based on the association of the at least one attribute with the file.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: January 14, 2025
    Assignee: SANDISK TECHNOLOGIES, INC.
    Inventors: Ramanathan Muthiah, Adarsh Sreedhar, Niraj Srimal
  • Publication number: 20250014031
    Abstract: A method for scoring authenticity of a non-fungible token (NFT) using multiple, disparate data sets includes: receiving a scoring request for the NFT; determining a marketplace authenticity score for a marketplace where the NFT is available for purchase based on marketplace metrics; determining a visual authenticity score based on a comparison of visual features of the NFT to visual features of trusted NFTs; determining a wallet authenticity score for a blockchain wallet associated with ownership of the NFT based on a transaction history for the blockchain wallet; calculating a confidence score for the NFT based on a combination of the marketplace, visual, and wallet authenticity scores, the confidence score representing a likelihood that the NFT is authentic; and transmitting the calculated confidence score in response to the received scoring request.
    Type: Application
    Filed: July 5, 2023
    Publication date: January 9, 2025
    Inventors: Garima ARORA, Adarsh PATANKAR