Patents by Inventor ADARSH

ADARSH has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12119198
    Abstract: In embodiments, systems and apparatus comprise a bracket having a through hole configured to receive a first connector connected to a panel spaced from the bracket, the bracket movable between first and second positions; a switch mountable on the panel, the switch having first and second switch positions; and at least one compression spring extending from the bracket to bias the bracket into the first position spaced away from the switch. When the bracket is in the first position, the switch is in the first switch position, and when the bracket is in the second position, the bracket engages and actuates the switch into the second switch position. The bracket is movable into the second position to engage and actuate the switch by coupling a second connector to the first connector. The switch is configured to trigger a signal indicating that the first connector is connected to the second connector.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: October 15, 2024
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Vijay Singh, Kumaresan Nagarajan, Adarsh Balareddy
  • Patent number: 12114000
    Abstract: A video decoder may apply a first inverse residual modification function to first decoded modified chroma residual data to generate first inverse modified chroma residual data. Additionally, the video decoder may apply a second inverse residual modification function to second decoded modified chroma residual data to generate second inverse modified chroma residual data. The first decoded modified chroma residual data is associated with a first chroma component and the second decoded modified chroma residual data is associated with a second chroma component. The video decoder may reconstruct a block of video data based on the first inverse modified chroma residual data and the second inverse modified chroma residual data.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: October 8, 2024
    Assignee: QUALCOMM INCORPORATED
    Inventors: Geert Van der Auwera, Bappaditya Ray, Adarsh Krishnan Ramasubramonian, Muhammed Zeyd Coban, Luong Pham Van, Marta Karczewicz
  • Publication number: 20240332177
    Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, where a smallest unit shape of three nearest neighbor memory openings is a non-equilateral triangle, and memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a vertical semiconductor channel and a vertical stack of memory elements.
    Type: Application
    Filed: July 31, 2023
    Publication date: October 3, 2024
    Inventors: Ryo NAKAMURA, Fei ZHOU, Rahul SHARANGPANI, Adarsh RAJASHEKHAR, Raghuveer S. MAKALA
  • Publication number: 20240331205
    Abstract: An example device for coding point cloud data includes: a memory configured to store point cloud data; and one or more processors implemented in circuitry and configured to: decode encoded point cloud geometry data for a point cloud to reconstruct point cloud geometry data for the point cloud; downscale the point cloud geometry data to form downscaled point cloud geometry data; and code attribute data for the point cloud using the downscaled point cloud geometry. When encoding the attribute data, the processors may encode the point cloud geometry data using a deep learning-based geometry encoder. When decoding the attribute data, the processors may upscale the downscaled point cloud attribute data. The processors may code a value representing an amount of downscaling to apply to the decoded point cloud geometry data.
    Type: Application
    Filed: April 2, 2024
    Publication date: October 3, 2024
    Inventors: Anique Akhtar, Geert Van der Auwera, Adarsh Krishnan Ramasubramonian, Marta Karczewicz
  • Publication number: 20240317336
    Abstract: A robot comprises a body comprising a scalable joint module having a housing including an actuator within the housing powered by a voltage regulator on the housing and defining a female connector cavity of the housing; a first plurality of axial thrust roller bearings on the housing and a second plurality of axial thrust roller bearings on an opposite side of the housing, wherein each of the first and second plurality of axial thrust roller bearings are sandwiched between two washers; a male connector opposite from the female connector cavity; a head module coupled to the body, containing an onboard computing system controlling the movement of the lunar exploration robot, and an actuated latching mechanism; and a tail module coupled to the body, wherein the tail module defines a cavity configured for the actuated latching mechanism of the head module to enter, to thereby couple the head and tail modules.
    Type: Application
    Filed: March 15, 2024
    Publication date: September 26, 2024
    Inventors: Alireza Ramezani, Matthew Schroeter, Ian McCarthy, Adarsh Salagame
  • Patent number: 12096835
    Abstract: An epilating device for extracting hairs out of a user's skin, including hair-clamping elements that are arranged adjacent to each other and rotatable relative to a housing. A drive system rotates the hair-clamping elements which co-operate in pairs and are moveable relative to each other during rotation. On each side surface facing an adjacent hair-clamping element, there is a hair-clamping section and a hair-catching section. The hair-catching sections of adjacent hair-clamping elements define a funnel area, wherein the hair-catching sections converge towards each other for guiding hairs towards the hair-clamping sections. The hair-clamping sections of adjacent hair-clamping elements are movable relative to each other from an open position, where the hair-clamping sections are at a distance from each other, to a closed position, where the hair-clamping sections are in mutual clamping engagement in a hair-clamping area.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: September 24, 2024
    Assignee: KONINKLIJKE PHILIPS N.V.
    Inventors: Robbert Freerk Johan Van Der Scheer, Joost Tomas Glazenburg, Geert Willem De Goeij, Adarsh Shrivastava, Johannes Beugels
  • Publication number: 20240312067
    Abstract: A method of encoding a point cloud includes determining, by one or more processors, a quantity of lasers used to capture light detection and ranging (LIDAR) data that represents the point cloud; and encoding, by the one or more processors, a laser index for a current node of the point cloud, wherein encoding the laser index comprises: obtaining a predicted laser index value of the current node; determining a residual laser index value for the current node, wherein determining the residual laser index value comprises constraining a sum of the residual laser index value and the predicted laser index value to be less than or equal to the determined quantity of lasers minus one; and encoding, in a bitstream, one or more syntax elements that represent the residual laser index value.
    Type: Application
    Filed: May 29, 2024
    Publication date: September 19, 2024
    Inventors: Adarsh Krishnan Ramasubramonian, Bappaditya Ray, Geert Van der Auwera, Marta Karczewicz
  • Publication number: 20240314358
    Abstract: A method of decoding point cloud data comprises obtaining a bitstream that is encoded to comply with one or more constraints and decoding the bitstream, wherein decoding the bitstream comprises: determining a residual value of a first component of an attribute of a point; generating a predicted value of a second component of the attribute of the point; and reconstructing the second component as a sum of the predicted value of the second component and a multiplication product of a scale factor for the second component and the residual value of the first component, wherein the constraints include a constraint that limits the first component of the attribute of the point, the residual value of the first component of the attribute of the point, the second component of the attribute, and the residual value of the second component of the attribute of the point to one or more predefined bitdepths.
    Type: Application
    Filed: May 24, 2024
    Publication date: September 19, 2024
    Inventors: Adarsh Krishnan Ramasubramonian, Luong Pham Van, Bappaditya Ray, Louis Joseph Kerofsky, Geert Van der Auwera, Marta Karczewicz
  • Patent number: 12096636
    Abstract: A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric portions may contain air gaps. A bit-line-contact via structure can be formed on top of a bit line. In some embodiments, dielectric cap strips may be located on top surface of the dielectric portions and may cover peripheral regions of the top surfaces of the bit lines without covering middle regions of the top surfaces of the bit lines.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: September 17, 2024
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Adarsh Rajashekhar, Raghuveer S. Makala, Rahul Sharangpani, Fei Zhou
  • Publication number: 20240303869
    Abstract: A device for encoding point cloud data, the device comprising: a memory to store the point cloud data; and one or more processors coupled to the memory and implemented in circuitry, the one or more processors configured to: determine a horizontal plane position of a node, wherein the horizontal plane position indicates a position of a single plane that is perpendicular to a first axis of a coordinate system, wherein the first axis is a horizontal axis; determine, from a plurality of contexts consisting of 8 contexts, a context for the horizontal plane position of the node; and perform arithmetic encoding on a syntax element indicating the horizontal plane position using the determined context.
    Type: Application
    Filed: April 4, 2024
    Publication date: September 12, 2024
    Inventors: Geert Van der Auwera, Bappaditya Ray, Adarsh Krishnan Ramasubramonian, Marta Karczewicz
  • Publication number: 20240295882
    Abstract: The present disclosure provides methods, apparatuses, systems, and computer-readable mediums for classifying a region and an intensity of a contact. A method includes obtaining, from a plurality of acoustic sensors provided on an inner surface of a bumper of the apparatus, a combined acoustic signal, the combined acoustic signal being based on an input signal provided to the plurality of acoustic sensors, determining, using a trained machine learning model that has been trained with acoustic signals and corresponding position and intensity information of impacts on a plurality of regions of an outer surface of the bumper, the region of the contact on the bumper with respect to the plurality of regions and the intensity of the contact, based on the combined acoustic signal, and determining a motion of the apparatus based on the region of the contact, the intensity of the contact, and an operating mode of the apparatus.
    Type: Application
    Filed: December 15, 2023
    Publication date: September 5, 2024
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Adarsh K. KOSTA, Alexis M. Burns, Caleb Escobedo, Siddharth Rupavatharam, Richard E. Howard, Lawrence Jackel, Daewon Lee, Ibrahim Volken Isler
  • Patent number: 12066282
    Abstract: A lighting stage includes a plurality of lights that project alternating spherical color gradient illumination patterns onto an object or human performer at a predetermined frequency. The lighting stage also includes a plurality of cameras that capture images of an object or human performer corresponding to the alternating spherical color gradient illumination patterns. The lighting stage also includes a plurality of depth sensors that capture depth maps of the object or human performer at the predetermined frequency. The lighting stage also includes (or is associated with) one or more processors that implement a machine learning algorithm to produce a three-dimensional (3D) model of the object or human performer. The 3D model includes relighting parameters used to relight the 3D model under different lighting conditions.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: August 20, 2024
    Assignee: GOOGLE LLC
    Inventors: Sean Ryan Francesco Fanello, Kaiwen Guo, Peter Christopher Lincoln, Philip Lindsley Davidson, Jessica L. Busch, Xueming Yu, Geoffrey Harvey, Sergio Orts Escolano, Rohit Kumar Pandey, Jason Dourgarian, Danhang Tang, Adarsh Prakash Murthy Kowdle, Emily B. Cooper, Mingsong Dou, Graham Fyffe, Christoph Rhemann, Jonathan James Taylor, Shahram Izadi, Paul Ernest Debevec
  • Publication number: 20240276725
    Abstract: A memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, each including a respective vertical semiconductor channel and a vertical stack of memory elements, a contact via structure contacting a reference electrically conductive layer that is one of the electrically conductive layers, and at least one silicon oxide liner laterally surrounding a cylindrical portion of the contact via structure and contacting a laterally protruding portion of the contact via structure.
    Type: Application
    Filed: March 26, 2024
    Publication date: August 15, 2024
    Inventors: Adarsh RAJASHEKHAR, Senaka KANAKAMEDALA, Koichi MATSUNO
  • Publication number: 20240262709
    Abstract: According to various embodiments, a method of quickly and inexpensively forming a crystallographically-stable, highly durable, cobalt-free, lithium-substituted, lithium-rich metal oxide (S-LRMO) material is provided, where the element that is used to replace lithium is some combination of Na, K, Ca, and Mg, and is above the levels commonly thought of as doping. In some embodiments, a cathode active material comprising a lithium-substituted, lithium-rich metal oxide is provided. For example, in some embodiments, the cathode active material comprises a chemical formula Li[LixAyMz]Ob, where A comprises at least one of Na, K, Ca and/or Mg. In some embodiments, (x+y) is greater than 0 and less than 0.3, y>0.05, z=1?(x+y), M includes Mn and Ni, and b is greater than or equal to 1.8 and less than or equal to 2.2.
    Type: Application
    Filed: January 31, 2024
    Publication date: August 8, 2024
    Applicant: Stratus Materials Inc.
    Inventors: Jay F. Whitacre, Jared Mitchell, Adarsh Rajesh Dave
  • Patent number: 12056103
    Abstract: The present application describes a database performance and usage footprint monitoring and analysis platform and related user application, which may provide insights across the whole of an enterprise's database inventory to increase visibility, accountability, and efficiency. The platform and related application may provide insight into enterprise database footprint and utilization, including displaying the data and associated metrics and analysis in a customizable interface. The platform may ingest and capture performance data and events to provide resource properties and cost analyses across enterprise groups. Future performance may be predicted by the platform, future data trends identified, and platform may provide usage prediction, perform root cause analysis to recommend action items, and provide alerts, among other functions.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: August 6, 2024
    Assignee: Target Brands, Inc.
    Inventors: Saravanan Kandasamy, Prajakta Deshpande, Deepa Sarasamma, Payal Verma, Sudha Adarsh
  • Publication number: 20240256727
    Abstract: Systems, articles of manufacture, apparatus, and methods are disclosed for machine-learning based hole plug validation. An example apparatus includes at least one memory, machine-readable instructions, and processor circuitry to at least one of execute or instantiate the machine-readable instructions to at least execute a machine-learning model based on an image of an aircraft component to generate an output representative of first identifications of first hole plugs in the aircraft component. The processor circuitry is further to determine one or more differences between the first identifications of the first hole plugs in the image and second identifications of second hole plugs in a reference model of the aircraft component. Additionally, the processor circuitry is to cause an operation associated with an aircraft to occur based on the one or more differences.
    Type: Application
    Filed: January 16, 2023
    Publication date: August 1, 2024
    Inventors: Seema Chopra, Ganesha P. Saralikana, Chandrashekhar, Adarsh Vittal Shetty, SK Sahariyaz Zaman
  • Publication number: 20240256446
    Abstract: Techniques for implementing a hardware-based cache controller in, e.g., a tiered memory computer system are provided. In one set of embodiments, the cache controller can flexibly operate in a number of different modes that aid the OS/hypervisor of the computer system in managing and optimizing its use of the system's memory tiers. In another set of embodiments, the cache controller can implement a hardware architecture that enables it to significantly reduce the probability of tag collisions, decouple cache capacity management from cache lookup and allocation, and handle multiple concurrent cache transactions.
    Type: Application
    Filed: January 26, 2023
    Publication date: August 1, 2024
    Inventors: Andreas Georg Nowatzyk, Pratap Subrahmanyam, Isam Wadih Akkawi, Adarsh Seethanadi Nayak, Nishchay Dua
  • Publication number: 20240256439
    Abstract: Techniques for implementing a hardware-based cache controller in, e.g., a tiered memory computer system are provided. In one set of embodiments, the cache controller can flexibly operate in a number of different modes that aid the OS/hypervisor of the computer system in managing and optimizing its use of the system's memory tiers. In another set of embodiments, the cache controller can implement a hardware architecture that enables it to significantly reduce the probability of tag collisions, decouple cache capacity management from cache lookup and allocation, and handle multiple concurrent cache transactions.
    Type: Application
    Filed: January 26, 2023
    Publication date: August 1, 2024
    Inventors: Andreas Georg Nowatzyk, Pratap Subrahmanyam, Isam Wadih Akkawi, Adarsh Seethanadi Nayak, Nishchay Dua
  • Publication number: 20240256459
    Abstract: A memory hierarchy includes a first memory and a second memory that is at a lower position in the memory hierarchy than the first memory. A method of managing the memory hierarchy includes: observing, over a first period of time, accesses to pages of the first memory; in response to determining that no page in a first group of pages was accessed during the first period of time, moving each page in the first group of pages from the first memory to the second memory; and in response to determining that the number of pages in other groups of pages of the first memory, which were accessed during the first period of time, is less than a threshold number of pages, moving each page in the other group of pages, that was not accessed during the first period of time from the first memory to the second memory.
    Type: Application
    Filed: January 26, 2023
    Publication date: August 1, 2024
    Inventors: Pratap SUBRAHMANYAM, Venkata Subhash Reddy PEDDAMALLU, Isam Wadih AKKAWI, Andreas Georg NOWATZYK, Rajesh VENKATASUBRAMANIAN, Yijiang YUAN, Adarsh Seethanadi NAYAK, Nishchay DUA, Sreekanth SETTY
  • Publication number: 20240256453
    Abstract: Techniques for implementing a hardware-based cache controller in, e.g., a tiered memory computer system are provided. In one set of embodiments, the cache controller can flexibly operate in a number of different modes that aid the OS/hypervisor of the computer system in managing and optimizing its use of the system's memory tiers. In another set of embodiments, the cache controller can implement a hardware architecture that enables it to significantly reduce the probability of tag collisions, decouple cache capacity management from cache lookup and allocation, and handle multiple concurrent cache transactions.
    Type: Application
    Filed: January 26, 2023
    Publication date: August 1, 2024
    Inventors: Andreas Georg Nowatzyk, Pratap Subrahmanyam, Isam Wadih Akkawi, Adarsh Seethanadi Nayak, Nishchay Dua