Amplifier bandwidth extension for high-speed tranceivers
There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.
Latest Broadcom Corporation Patents:
1. Field of the Invention
The present invention relates generally to data transmission. More particularly, the present invention relates to amplifier/buffer bandwidth extension for high-speed tranceivers.
2. Background Art
There is a continuous push in the art to provide higher bandwidth data links for fast and large volume data transfer. With the increased proliferation of digital data including images, video, and other data, the need to quickly transfer digital data from one location to another becomes increasingly important. For example, high-speed data links are necessary to send video signals to a display, to transfer data across networks, to archive data to disks, and to perform other tasks.
For high-speed tranceivers with data rates exceeding 45 Gbs/s, quarter rate architecture is often used to relax the speed constraints for critical decision circuits such as samplers and slicers. However, this architecture poses some implementation challenges. Specifically, to acquire four data bits and four edge bits to create an optimal sampling point for the clock data recovery (CDR), eight parallel samplers and slicers are needed. This heavy load poses difficulties in amplifier/buffer design, as conventional bandwidth extension techniques cannot provide sufficient gain and bandwidth boosting to meet the amplitude and jitter specifications required by the samplers and slicers.
Accordingly, there is a need to overcome the drawbacks and deficiencies in the art by providing an amplifier design suitable for high-speed transceivers with increasing data rate and heavier load.
SUMMARY OF THE INVENTIONThere is provided a high bandwidth extension technique with a variety of applications, such as amplifier/buffer, drivers, comparators, multiplexers and others, substantially as shown in and/or described in connection with at least one of the figures, as set forth more completely in the claims.
The features and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, wherein:
The present application is directed to a high bandwidth amplifier/buffer for high-speed transceivers such as with data rate exceeding 45 Gbs/s. The following description contains specific information pertaining to the implementation of the present invention. One skilled in the art will recognize that the present invention may be implemented in a manner different from that specifically discussed in the present application. Moreover, some of the specific details of the invention are not discussed in order not to obscure the invention. The specific details not described in the present application are within the knowledge of a person of ordinary skill in the art. The drawings in the present application and their accompanying detailed description are directed to merely exemplary embodiments of the invention. To maintain brevity, other embodiments of the invention, which use the principles of the present invention, are not specifically described in the present application and are not specifically illustrated by the present drawings.
As shown in diagram 100a, shunt inductance element 105 is coupled with voltage supply point 102, which is connected to voltage supply 101. Shunt inductance element 105 is connected to resistor 110 and resistor 115. Resistor 110 is connected to first terminal of transistor 120. Resistor 110, transistor 120 and capacitor 148 are coupled to output point 151. Resistor 115 is connected to the first terminal of transistor 125. Resistor 115, transistor 125, and capacitor 149 are coupled to output point 156. Capacitors 148 and 149 are connected to ground 190. The second terminals of transistor 120 and 125 are coupled at connection point 106. The first terminal of transistor 130 is connected to connection point 106 and the second terminal of transistor 130 is connected to ground 190.
As the signal frequency increases, shunt inductance element 105 introduces a component that increases the impedance in the circuit, offsetting the decreased impedance caused by load capacitor 148 and 149. However, the inductance value of shunt inductance element 105 must be optimized to keep data jitter within manageable levels. As a result, the shunt peaking implemented in diagram 100a may only extend bandwidth by a factor of approximately one and a half (1.5) times.
Moving to
Comparing diagram 100a of
The t-coil peaking implemented in diagram 100b of
Moving to
Diagram 100c of
As with shunt peaking and t-coil peaking, the series peaking implemented in diagram 100c of
Accordingly,
With respect to
Diagram 200a of
While the amplifier embodiment shown in diagram 200a of
With respect to
Comparing diagram 200b of
Furthermore, while diagram 200b of
Load capacitors 241a-241d may have a total capacitance equal to the capacitance of load capacitor 248 of
As shown in diagram 200b of
At high data rates such as 45 gigabits per second (Gbs/s) and above, each of inductance element 239a-239d and 240a-240d may comprise a high impedance transmission line rather than a discrete inductor. Thus, the high impedance transmission lines are equivalent to inductance components, absorbing the parasitic capacitance from the metal structure as well as from the amplifier device itself.
The amplifier circuit in diagram 200b of
With respect to
Diagram 200c of
The first and second perfect binary tree structures 203 and 204 have the properties of a perfect binary tree, as known in the art. Thus, it can be seen that for perfect binary tree structure 203, inductance element 270 corresponds to the root node, inductance elements 271 and 272 correspond to child nodes of the root node, portions 231 and 232 correspond to leaf nodes with a parent inductance element 271, and portions 233 and 234 correspond to leaf nodes with a parent inductance element 272. Second perfect binary tree structure 204 is constructed in a similar manner, as shown in diagram 200c of
Similar to
Moving to
With respect to
Diagram 200d of
Thus, inductance element 270-275, 239a-239d and 240a-240d of
Thus, several high bandwidth amplifier designs for high-speed transceivers have been disclosed. By splitting the load capacitor into several equal parts, data bandwidth may be extended well beyond 45 Gbs/s. Further, by combining various bandwidth extension techniques such as t-coil peaking, shunt peaking, and series peaking, bandwidth may be further extended. Moreover, since the inductor and t-coil structures are easily identifiable, the capacitor splitting provides equal parts, and the inductance trees provide symmetrical structures, data identification at the next stage is advantageously simplified. Furthermore, while the disclosed examples have focused on data buffer amplifier circuit designs, a similar technique may also be applied to other circuit design structures such as high-speed multiplexers and high-speed samplers and slicers. Thus, the disclosed circuit is not limited to data buffer amplifier circuits and may also be utilized for a variety of high-speed transceiver applications.
From the above description of the invention it is manifest that various techniques can be used for implementing the concepts of the present invention without departing from its scope. Moreover, while the invention has been described with specific reference to certain embodiments, a person of ordinary skills in the art would recognize that changes can be made in form and detail without departing from the spirit and the scope of the invention. As such, the described embodiments are to be considered in all respects as illustrative and not restrictive. It should also be understood that the invention is not limited to the particular embodiments described herein, but is capable of many rearrangement, modifications, and substitutions without departing from the scope of the invention.
Claims
1. A circuit for high-speed transceivers, the circuit comprising:
- a first transistor having a first terminal connected to a first t-coil, a second terminal, and a third terminal;
- a second transistor having a first terminal connected to a second t-coil, a second terminal connected to the second terminal of the first transistor at a connection point, and a third terminal;
- a third transistor having a first terminal connected to the connection point, a second terminal connected to ground, and a third terminal;
- a plurality of portions including a first portion and a second portion, each of the plurality of portions comprising: a load capacitor connected from a voltage output point to ground; and an inductance element connected to the load capacitor at the voltage output point;
- wherein the first portion is further connected to the first t-coil, and wherein the second portion is further connected to the second t-coil.
2. The circuit of claim 1, further comprising:
- a first resistor connected between a voltage supply point and the first t-coil; and
- a second resistor connected between the voltage supply point and the second t-coil.
3. The circuit of claim 1, wherein the plurality of portions comprises:
- a first plurality of portions including the first portion, wherein an inductance element of each of the first plurality of portions is connected to the first t-coil; and
- a second plurality of portions including the second portion, wherein an inductance element of each of the second plurality of portions is connected to the second t-coil.
4. The circuit of claim 3, wherein a composition of the first plurality of portions is equivalent to a composition of the second plurality of portions.
5. The circuit of claim 4, wherein a count of the plurality of portions is eight.
6. The circuit of claim 3, further comprising:
- a first perfect binary tree structure comprising a first plurality of nodes each having an inductance element, the first plurality of nodes including: a root node connected to the first t-coil; and a plurality of leaf nodes corresponding to the first plurality of portions;
- a second perfect binary tree structure comprising a second plurality of nodes each having an inductance element, the second plurality of nodes including: a root node connected to the second t-coil; and a plurality of leaf nodes corresponding to the second plurality of portions.
7. The circuit of claim 6, wherein the inductance element of each of the first plurality of nodes and each of the second plurality of nodes is a high impedance transmission line.
8. The circuit of claim 6, wherein a composition of the first perfect binary tree structure is equivalent to a composition of the second perfect binary tree structure.
9. The circuit of claim 6, wherein a height of the first perfect binary tree structure and a height of the second perfect binary tree structure is two or more.
10. The circuit of claim 6, wherein a bandwidth at the output point of the plurality of portions is least 45 gigabits per second.
11. The circuit of claim 1, wherein the load capacitor of each of the plurality of portions comprise an equal load capacitance value.
12. The circuit of claim 1, wherein the inductance element of each of the plurality of portions is a high impedance transmission line.
13. The circuit of claim 1, wherein:
- the first terminal of the first transistor, the first terminal of the second transistor, and the first terminal of the third transistor is a drain;
- the second terminal of the first transistor, the second terminal of the second transistor, and the second terminal of the third transistor is a source; and
- the third terminal of the first transistor, the third terminal of the second transistor, and the third terminal of the third transistor is a gate.
14. A circuit for high-speed transceivers, the circuit comprising:
- a first transistor having a first terminal connected to a first t-coil, a second terminal, and a third terminal;
- a second transistor having a first terminal connected to a second t-coil, a second terminal connected to the second terminal of the first transistor at a connection point, and a third terminal;
- a third transistor having a first terminal connected to the connection point, a second terminal connected to ground, and a third terminal;
- a plurality of portions including a first plurality of portions and a second plurality of portions, each of the plurality of portions comprising: a load capacitor connected to ground; and an inductance element connected to the capacitor at an output point;
- wherein the first plurality of portions is further connected to the first t-coil, and wherein the second plurality of portions is further connected to the second t-coil.
15. The circuit of claim 14, further comprising:
- a first resistor connected between a voltage supply point and the first t-coil;
- a second resistor connected between the voltage supply point and the second t-coil.
16. The circuit of claim 14, wherein a composition of the first plurality of portions is equivalent to a composition of the second plurality of portions.
17. The circuit of claim 14, further comprising:
- a first perfect binary tree structure comprising a first plurality of nodes each having an inductance element, the first plurality of nodes including: a root node connected to the first t-coil; and a plurality of leaf nodes corresponding to the first plurality of portions;
- a second perfect binary tree structure comprising a second plurality of nodes each having an inductance element, the second plurality of nodes including: a root node connected to the second t-coil; and a plurality of leaf nodes corresponding to the second plurality of portions.
18. The circuit of claim 17, wherein the inductance element of each of the plurality of portions, of each of the first plurality of nodes, and of each of the second plurality of nodes is a high impedance transmission line.
5936458 | August 10, 1999 | Rylov |
6985036 | January 10, 2006 | Bhattacharjee et al. |
7902900 | March 8, 2011 | Liu et al. |
20090009244 | January 8, 2009 | Banba |
20120098572 | April 26, 2012 | Tripathi et al. |
Type: Grant
Filed: Jun 22, 2011
Date of Patent: May 28, 2013
Patent Publication Number: 20120326788
Assignee: Broadcom Corporation (Irvine, CA)
Inventors: Delong Cui (Tustin, CA), Afshin Momtaz (Laguna Hills, CA), Jun Cao (Irvine, CA)
Primary Examiner: Crystal L Hammond
Application Number: 13/166,592
International Classification: H03F 3/16 (20060101); H03F 3/04 (20060101);