Patents by Inventor Ajey Poovannummoottil Jacob

Ajey Poovannummoottil Jacob has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9716174
    Abstract: A semiconductor stack of a FinFET in fabrication includes a bulk silicon substrate, a selectively oxidizable sacrificial layer over the bulk substrate and an active silicon layer over the sacrificial layer. Fins are etched out of the stack of active layer, sacrificial layer and bulk silicon. A conformal oxide deposition is made to encapsulate the fins, for example, using a HARP deposition. Relying on the sacrificial layer having a comparatively much higher oxidation rate than the active layer or substrate, selective oxidization of the sacrificial layer is performed, for example, by annealing. The presence of the conformal oxide provides structural stability to the fins, and prevents fin tilting, during oxidation. Selective oxidation of the sacrificial layer provides electrical isolation of the top active silicon layer from the bulk silicon portion of the fin, resulting in an SOI-like structure. Further fabrication may then proceed to convert the active layer to the source, drain and channel of the FinFET.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: July 25, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Murat Kerem Akarvardar, Jody A. Fronheiser, Ajey Poovannummoottil Jacob
  • Publication number: 20170194245
    Abstract: A method of providing on-chip capacitance includes providing a starting interconnect structure for semiconductor device(s), the starting interconnect structure including a layer of dielectric material. Vias of a same cross-sectional shape are formed in the layer of dielectric material having different and successive geometric cross-sectional size, and capacitors matching the via shape are formed in the vias. The geometric cross-sectional shapes include circles, squares, hexagons and octagons. For the non-circle shapes, a capacitance thereof is approximated by the capacitance of a coaxial capacitor fitting within and touching all sides of the non-circle shape multiplied by a correction factor of about 0.01 to about 2.
    Type: Application
    Filed: January 4, 2016
    Publication date: July 6, 2017
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Suraj PATIL, Ajey Poovannummoottil JACOB, Shesh Mani PANDEY
  • Patent number: 9698025
    Abstract: A method includes forming at least one fin on a semiconductor substrate. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the top surface of the fin. A substantially vertical nanowire is formed on the exposed top surface. At least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: July 4, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Steven Bentley, Richard A. Farrell, Gerard Schmid, Ajey Poovannummoottil Jacob
  • Patent number: 9673222
    Abstract: Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: June 6, 2017
    Assignees: GLOBALFOUNDRIES Inc., STMicroelectronics, Inc., International Business Machines Corporation
    Inventors: Ajey Poovannummoottil Jacob, Kangguo Cheng, Bruce Doris, Nicolas Loubet, Prasanna Khare, Rama Divakaruni
  • Patent number: 9673083
    Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, the fin having a lower first section that contains an oxidation-retarding implant region and an upper second section that is substantially free of the oxidation-retarding implant region, forming a sidewall spacer on opposite sides of the upper portion of the fin, forming a first layer of insulating material adjacent the sidewall spacers and the upper second section of the lower portion of the fin, and, with the first layer of insulating material in position, performing a thermal anneal process to convert the portion of the upper second section of the fin that is in contact with the first layer of insulating material into an oxide fin isolation region positioned under the fin above the lower first section of the fin.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: June 6, 2017
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ajey Poovannummoottil Jacob, Bruce Doris, Kangguo Cheng, Ali Khakifirooz, Kern Rim
  • Publication number: 20170141227
    Abstract: One method disclosed includes forming first, second and third fins for a first NMOS device, a PMOS device and a second NMOS device, respectively. According to this method, the first fin consists entirely of the substrate material, the second and third fins comprise a lower substrate fin portion made of the substrate material and an upper fin portion made of a second semiconductor material and a third semiconductor material, respectively, wherein the second semiconductor material and the third semiconductor material are each different from the substrate material. The method also includes forming a semiconductor material cladding on the exposed upper portion of the third fin for the second NMOS FinFET device.
    Type: Application
    Filed: November 13, 2015
    Publication date: May 18, 2017
    Inventor: Ajey Poovannummoottil Jacob
  • Publication number: 20170141226
    Abstract: One illustrative method disclosed herein includes, among other things, forming first and second fins, respectively, for a PMOS device and an NMOS device, each of the first and second fins comprising a lower substrate fin portion made of the substrate material and an upper fin portion that is made of a second semiconductor material that is different from the substrate material, exposing at least a portion of the upper fin portion of both the first and second fins, masking the PMOS device and forming a semiconductor material cladding on the exposed upper portion of the second fin for the NMOS device, wherein the semiconductor material cladding is a different semiconductor material than that of the second semiconductor material. The method also including forming gate structures for the PMOS FinFET device and the NMOS FinFET device.
    Type: Application
    Filed: November 13, 2015
    Publication date: May 18, 2017
    Inventor: Ajey Poovannummoottil Jacob
  • Publication number: 20170125361
    Abstract: A semiconductor structure includes a dielectric layer, a silicidable metal layer and an undoped filler material layer are used to create an anti-efuse device. The anti-efuse device may be situated in a dielectric layer of an interconnect structure for a semiconductor device or may be planar. Where part of an interconnect structure, the anti-efuse device may be realized by causing a current to flow therethrough while applying local heating. Where planar, the filler material may be situated between extensions of metal pads and metal atoms caused to move from the extensions to the filler material layer using a current flow and local heating.
    Type: Application
    Filed: October 29, 2015
    Publication date: May 4, 2017
    Applicant: GLOBALFOUNDRIES Inc.
    Inventors: Suraj K. PATIL, Min-hwa CHI, Ajey Poovannummoottil JACOB
  • Patent number: 9633947
    Abstract: A method includes forming a folding template in a first dielectric layer. The folding template has a plurality of surfaces that are positioned in different planes. A ballistic conductor line is formed on the plurality of surfaces of the folding template. A device includes a first dielectric layer and a vertically folded line disposed in the first dielectric layer, the vertically folded line including a ballistic conductor material.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: April 25, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ajey Poovannummoottil Jacob
  • Patent number: 9634123
    Abstract: A method includes forming a fin on a semiconductor substrate. An isolation structure is formed adjacent the fin. A silicon alloy material is formed on a portion of the fin extending above the isolation structure. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin and to define a first insulating layer separating the fin from the substrate.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: April 25, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ajey Poovannummoottil Jacob
  • Patent number: 9627245
    Abstract: One illustrative method disclosed herein involves, among other things, forming trenches to form an initial fin structure having an initial exposed height and sidewalls, forming a protection layer on at least the sidewalls of the initial fin structure, extending the depth of the trenches to thereby define an increased-height fin structure, with a layer of insulating material over-filling the final trenches and with the protection layer in position, performing a fin oxidation thermal anneal process to convert at least a portion of the increased-height fin structure into an isolation material, removing the protection layer, and performing an epitaxial deposition process to form a layer of semiconductor material on at least portions of the initial fin structure.
    Type: Grant
    Filed: March 5, 2014
    Date of Patent: April 18, 2017
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation, STMicroelectronics, Inc.
    Inventors: Ajey Poovannummoottil Jacob, Bruce Doris, Kangguo Cheng, Nicolas Loubet
  • Patent number: 9590040
    Abstract: One illustrative method disclosed herein includes, among other things, forming a sacrificial fin structure above a semiconductor substrate, forming a layer of insulating material around the sacrificial fin structure, removing the sacrificial fin structure so as to define a replacement fin cavity in the layer of insulating material that exposes an upper surface of the substrate, forming a replacement fin in the replacement fin cavity on the exposed upper surface of the substrate, recessing the layer of insulating material, and forming a gate structure around at least a portion of the replacement fin exposed above the recessed layer of insulating material.
    Type: Grant
    Filed: July 25, 2014
    Date of Patent: March 7, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Murat Kerem Akarvardar, Ajey Poovannummoottil Jacob
  • Patent number: 9589849
    Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of initial fins that have the same initial axial length and the same initial strain above a substrate, performing at least one etching process so as to cut a first fin to a first axial length and to cut a second fin to a second axial length that is less than the first axial length, wherein the cut first fin retains a first amount of the initial strain and the cut second fin retains about zero of the initial strain or a second amount of the initial strain that is less than the first amount, and forming gate structures around the first and second cut fins to form FinFET devices.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: March 7, 2017
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar, Bruce Doris, Ali Khakifirooz
  • Patent number: 9570244
    Abstract: Embodiments of the present disclosure relate to a solid-state supercapacitor. The solid-state supercapacitor includes a first electrode, a second electrode, and a solid-state ionogel structure between the first electrode and the second electrode. The solid-state ionogel structure prevents direct electrical contact between the first electrode and the second electrode. Further, the solid-state ionogel structure substantially fills voids inside the first electrode and the second electrode.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: February 14, 2017
    Assignee: The Regents of the University of California
    Inventors: Bruce S. Dunn, Chi On Chui, Ajey Poovannummoottil Jacob, Daniel Membreno, Leland Smith
  • Patent number: 9564486
    Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: February 7, 2017
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES INC., RENESAS ELECTRONICS CORPORATION
    Inventors: Murat Kerem Akarvardar, Steven John Bentley, Kangguo Cheng, Bruce B. Doris, Jody Fronheiser, Ajey Poovannummoottil Jacob, Ali Khakifirooz, Toshiharu Nagumo
  • Patent number: 9524908
    Abstract: One illustrative method disclosed herein includes, among other things, forming a region of a sacrificial material in a semiconductor substrate at a location where the portion of the fin to be removed will be located, after forming the region of sacrificial material, performing at least one first etching process to form a plurality of fin-formation trenches that define the fin, wherein at least a portion of the fin is comprised of the sacrificial material, and performing at least one second etching process to selectively remove substantially all of the sacrificial material portion of the fin relative to the substrate.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: December 20, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yi Qi, Ajey Poovannummoottil Jacob
  • Patent number: 9508853
    Abstract: One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming a sacrificial gate structure around a portion of an initial fin, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure and removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove portions of the initial fin so as to thereby define a reduced size fin and recesses under the sidewall spacers, forming at least one replacement epi semiconductor cladding material around the reduced size fin in the replacement gate cavity and in the recesses under the sidewall spacers, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: November 29, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Witold P. Maszara, Jody A. Fronheiser
  • Patent number: 9496354
    Abstract: One illustrative method disclosed herein includes removing the sidewall spacers and a gate cap layer so as to thereby expose an upper surface and sidewalls of a sacrificial gate structure, forming an etch stop layer above source/drain regions of a device and on the sidewalls and upper surface of the sacrificial gate structure, forming a first layer of insulating material above the etch stop layer, removing the sacrificial gate structure so as to define a replacement gate cavity that is laterally defined by portions of the etch stop layer, forming a replacement gate structure in the replacement gate cavity, and forming a second gate cap layer above the replacement gate structure.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: November 15, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Xiuyu Cai, Ajey Poovannummoottil Jacob, Andreas Knorr, Christopher Prindle
  • Patent number: 9484428
    Abstract: A semiconductor device includes a first gate electrode defined on a base layer. A first plurality of layers is disposed on a first sidewall of the first gate electrode. The first plurality of layers includes a first dielectric layer formed on the first sidewall, a first ballistic conductor layer formed above the first dielectric layer, an intermediate layer formed above the first ballistic conductor layer, a second ballistic conductor layer formed above the intermediate layer, and a second dielectric layer formed above the second ballistic conductor layer. A second gate electrode contacts the second dielectric layer.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: November 1, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ajey Poovannummoottil Jacob
  • Patent number: 9478663
    Abstract: A method includes forming a fin on a semiconductor substrate and forming recesses on sidewalls of the fin. A silicon alloy material is formed in the recesses. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin. A semiconductor device includes a substrate, a fin defined on the substrate and an isolation structure disposed adjacent the fin. A first portion of the fin extending above the isolation structure has a substantially vertical sidewall and a different material composition than a second portion of the fin not extending above the isolation structure.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Jody A. Fronheiser, Yi Qi, Sylvie Mignot