Abstract: One illustrative method disclosed herein includes, among other things, recessing first and second fins to define replacement fin cavities in a layer of insulating material, forming an initial strain relaxed buffer layer such that it only partially fills the replacement fin cavities, implanting carbon into the initial strain relaxed buffer layer in the NMOS region, forming a channel semiconductor material on the initial strain relaxed buffer layer within the replacement fin cavities in both the NMOS region and the PMOS region to thereby define an NMOS fin comprised of the channel semiconductor material and a carbon-doped strain relaxed buffer layer and a PMOS fin comprised of the channel semiconductor material and the initial strain relaxed buffer layer and forming gate structures for the NMOS and PMOS devices.

Abstract: One illustrative method disclosed herein includes, among other things, forming a composite fin structure that is comprised of a first germanium-containing semiconductor material having a first concentration of germanium and a tensile-strained second semiconductor material (having a lesser germanium concentration) positioned on the first germanium-containing semiconductor material and performing a thermal anneal process to convert the first germanium-containing semiconductor material portion of the composite fin structure into a germanium-containing oxide isolation region positioned under the second semiconductor material that is a tensile-strained final fin for an NMOS FinFET device.

Abstract: A semiconductor device includes a first gate electrode defined on a base layer. A first plurality of layers is disposed on a first sidewall of the first gate electrode. The first plurality of layers includes a first dielectric layer formed on the first sidewall, a first ballistic conductor layer formed above the first dielectric layer, an intermediate layer formed above the first ballistic conductor layer, a second ballistic conductor layer formed above the intermediate layer, and a second dielectric layer formed above the second ballistic conductor layer. A second gate electrode contacts the second dielectric layer.

Abstract: One illustrative method disclosed herein includes, among other things, forming a fin in a semiconductor substrate, the fin having a lower first section that contains an oxidation-retarding implant region and an upper second section that is substantially free of the oxidation-retarding implant region, forming a sidewall spacer on opposite sides of the upper portion of the fin, forming a first layer of insulating material adjacent the sidewall spacers and the upper second section of the lower portion of the fin, and, with the first layer of insulating material in position, performing a thermal anneal process to convert the portion of the upper second section of the fin that is in contact with the first layer of insulating material into an oxide fin isolation region positioned under the fin above the lower first section of the fin.

Abstract: A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate. A thermal process is performed to define a silicon alloy fin from the silicon alloy material and the fin and to define silicon alloy surface portions from the silicon alloy material and the exposed surface portions of the substrate. A semiconductor device includes a substrate, a fin defined on the substrate, the fin comprising a silicon alloy and having a substantially vertical sidewall, and silicon alloy surface portions on the substrate adjacent the fin.

Abstract: One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming a sacrificial gate structure around a portion of an initial fin, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure and removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove portions of the initial fin so as to thereby define a reduced size fin and recesses under the sidewall spacers, forming at least one replacement epi semiconductor cladding material around the reduced size fin in the replacement gate cavity and in the recesses under the sidewall spacers, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.

Abstract: A semiconductor device includes a source/drain region, a gate structure, a gate cap layer positioned above the gate structure and a sidewall spacer positioned adjacent to opposite sides of the gate structure. A first epi semiconductor material is positioned in the source/drain region, the first epi semiconductor material having a first lateral width at an upper surface thereof. A second epi semiconductor material is positioned on the first epi semiconductor material, the second epi semiconductor material extending laterally over and covering at least a portion of an uppermost end of the sidewall spacer and having a second lateral width at an upper surface thereof that is greater than the first lateral width. A metal silicide region is positioned on the upper surface of the second epi semiconductor material.

Abstract: A method includes forming at least one fin on a semiconductor substrate. A silicon alloy material is formed on the fin and on exposed surface portions of the substrate. A thermal process is performed to define a silicon alloy fin from the silicon alloy material and the fin and to define silicon alloy surface portions from the silicon alloy material and the exposed surface portions of the substrate. A semiconductor device includes a substrate, a fin defined on the substrate, the fin comprising a silicon alloy and having a substantially vertical sidewall, and silicon alloy surface portions on the substrate adjacent the fin.

Abstract: One device disclosed includes a gate structure positioned around a perimeter surface of the fin, a layer of channel semiconductor material having an axial length in the channel length direction of the device that corresponds approximately to the overall width of the gate structure being positioned between the gate structure and around the outer perimeter surface of the fin, wherein an inner surface of the layer of channel semiconductor material is spaced apart from and does not contact the outer perimeter surface of the fin. One method disclosed involves, among other things, forming first and second layers of semiconductor material around the fin, forming a gate structure around the second semiconductor material, removing the portions of the first and second layers of semiconductor material positioned laterally outside of sidewall spacers and removing the first layer of semiconductor material positioned below the second layer of semiconductor material.

Abstract: Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.

Abstract: A method includes forming a fin on a semiconductor substrate. An isolation structure is formed adjacent the fin. A silicon alloy material is formed on a portion of the fin extending above the isolation structure. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin and to define a first insulating layer separating the fin from the substrate.

Abstract: One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming an initial epi semiconductor cladding material around the exposed portion of a fin for an entire axial length of the fin, forming a sacrificial gate structure around a portion of the fin and the initial cladding material, removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove at least the exposed portion of the initial cladding material and thereby expose a surface of the fin within the replacement gate cavity, forming at least one replacement epi semiconductor cladding material around the exposed surface of the fin, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.

Abstract: One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming an initial epi semiconductor cladding material around the exposed portion of a fin for an entire axial length of the fin, forming a sacrificial gate structure around a portion of the fin and the initial cladding material, removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove at least the exposed portion of the initial cladding material and thereby expose a surface of the fin within the replacement gate cavity, forming at least one replacement epi semiconductor cladding material around the exposed surface of the fin, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.

Abstract: Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.

Abstract: One illustrative embodiment involves forming a plurality of trenches in a substrate so as to define a fin, forming a first oxidation-blocking layer of insulating material in the trenches so as to cover a portion, but not all, of the sidewalls of the lower portion of the fin, forming a second layer of insulating material above the first oxidation-blocking layer of insulating material, and performing a thermal anneal process to convert part, but not all, of the lower portion of the fin positioned above the first oxidation-blocking layer of insulating material into an oxide fin isolation region positioned under the fin.

Abstract: The present disclosure is directed to forming relatively abrupt junctions between the channel region and source/drain regions of a PMOS transistor device with a germanium-containing channel region. A liner layer is formed in previously formed source/drain cavities prior to the formation of epi semiconductor material in the source/drain cavities above the liner layer. The materials for the liner layer and, particularly, the concentration of germanium (if any is present) are adjusted relative to the germanium concentration in the channel region and the epi source/drain material such that, during an anneal process, dopant materials (e.g., boron) that diffuse from the source/drain region during the anneal process tend to accumulate in or near the liner layer.

Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.

Abstract: A method includes forming a fin on a semiconductor substrate and forming recesses on sidewalls of the fin. A silicon alloy material is formed in the recesses. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin. A semiconductor device includes a substrate, a fin defined on the substrate and an isolation structure disposed adjacent the fin. A first portion of the fin extending above the isolation structure has a substantially vertical sidewall and a different material composition than a second portion of the fin not extending above the isolation structure.

Abstract: One illustrative method disclosed herein includes, among other things, performing first and second in situ doping, epitaxial deposition processes to form first and second layers of in situ doped epi semiconductor material, respectively, above a semiconductor substrate, wherein one of the first and second layers has a high level of germanium and a low level of P-type dopant material and the other of the first and second layers has a low level of germanium and a high level of P-type dopant material, and performing a mixing thermal anneal process on the first and second layers so as to form the final silicon germanium material having a high level of germanium and a high level of P-type dopant material.

Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.