Patents by Inventor Ajey Poovannummoottil Jacob

Ajey Poovannummoottil Jacob has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Solid-state supercapacitor
    Patent number: 9570244
    Abstract: Embodiments of the present disclosure relate to a solid-state supercapacitor. The solid-state supercapacitor includes a first electrode, a second electrode, and a solid-state ionogel structure between the first electrode and the second electrode. The solid-state ionogel structure prevents direct electrical contact between the first electrode and the second electrode. Further, the solid-state ionogel structure substantially fills voids inside the first electrode and the second electrode.
    Type: Grant
    Filed: November 13, 2014
    Date of Patent: February 14, 2017
    Assignee: The Regents of the University of California
    Inventors: Bruce S. Dunn, Chi On Chui, Ajey Poovannummoottil Jacob, Daniel Membreno, Leland Smith
  • Self-aligned dual-height isolation for bulk FinFET
    Patent number: 9564486
    Abstract: A method of forming a semiconductor structure includes forming a first isolation region between fins of a first group of fins and between fins of a second group of fins. The first a second group of fins are formed in a bulk semiconductor substrate. A second isolation region is formed between the first group of fins and the second group of fins, the second isolation region extends through a portion of the first isolation region such that the first and second isolation regions are in direct contact and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk semiconductor substrate of the first isolation region.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: February 7, 2017
    Assignees: International Business Machines Corporation, GLOBALFOUNDRIES INC., RENESAS ELECTRONICS CORPORATION
    Inventors: Murat Kerem Akarvardar, Steven John Bentley, Kangguo Cheng, Bruce B. Doris, Jody Fronheiser, Ajey Poovannummoottil Jacob, Ali Khakifirooz, Toshiharu Nagumo
  • Methods of removing portions of fins by preforming a selectively etchable material in the substrate
    Patent number: 9524908
    Abstract: One illustrative method disclosed herein includes, among other things, forming a region of a sacrificial material in a semiconductor substrate at a location where the portion of the fin to be removed will be located, after forming the region of sacrificial material, performing at least one first etching process to form a plurality of fin-formation trenches that define the fin, wherein at least a portion of the fin is comprised of the sacrificial material, and performing at least one second etching process to selectively remove substantially all of the sacrificial material portion of the fin relative to the substrate.
    Type: Grant
    Filed: April 1, 2014
    Date of Patent: December 20, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Yi Qi, Ajey Poovannummoottil Jacob
  • Channel cladding last process flow for forming a channel region on a FinFET device having a reduced size fin in the channel region
    Patent number: 9508853
    Abstract: One method of forming epi semiconductor cladding materials in the channel region of a semiconductor device is disclosed which includes forming a sacrificial gate structure around a portion of an initial fin, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure and removing the sacrificial gate structure so as to thereby define a replacement gate cavity, performing an etching process through the replacement gate cavity to remove portions of the initial fin so as to thereby define a reduced size fin and recesses under the sidewall spacers, forming at least one replacement epi semiconductor cladding material around the reduced size fin in the replacement gate cavity and in the recesses under the sidewall spacers, and forming a replacement gate structure within the replacement gate cavity around the at least one replacement epi semiconductor cladding material.
    Type: Grant
    Filed: March 18, 2016
    Date of Patent: November 29, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Witold P. Maszara, Jody A. Fronheiser
  • Semiconductor devices with dummy gate structures partially on isolation regions
    Patent number: 9496354
    Abstract: One illustrative method disclosed herein includes removing the sidewall spacers and a gate cap layer so as to thereby expose an upper surface and sidewalls of a sacrificial gate structure, forming an etch stop layer above source/drain regions of a device and on the sidewalls and upper surface of the sacrificial gate structure, forming a first layer of insulating material above the etch stop layer, removing the sacrificial gate structure so as to define a replacement gate cavity that is laterally defined by portions of the etch stop layer, forming a replacement gate structure in the replacement gate cavity, and forming a second gate cap layer above the replacement gate structure.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: November 15, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Xiuyu Cai, Ajey Poovannummoottil Jacob, Andreas Knorr, Christopher Prindle
  • Non-planar exciton transistor (BiSFET) and methods for making
    Patent number: 9484428
    Abstract: A semiconductor device includes a first gate electrode defined on a base layer. A first plurality of layers is disposed on a first sidewall of the first gate electrode. The first plurality of layers includes a first dielectric layer formed on the first sidewall, a first ballistic conductor layer formed above the first dielectric layer, an intermediate layer formed above the first ballistic conductor layer, a second ballistic conductor layer formed above the intermediate layer, and a second dielectric layer formed above the second ballistic conductor layer. A second gate electrode contacts the second dielectric layer.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: November 1, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ajey Poovannummoottil Jacob
  • FinFET device including a uniform silicon alloy fin
    Patent number: 9478663
    Abstract: A method includes forming a fin on a semiconductor substrate and forming recesses on sidewalls of the fin. A silicon alloy material is formed in the recesses. A thermal process is performed to define a silicon alloy fin portion from the silicon alloy material and the fin. A semiconductor device includes a substrate, a fin defined on the substrate and an isolation structure disposed adjacent the fin. A first portion of the fin extending above the isolation structure has a substantially vertical sidewall and a different material composition than a second portion of the fin not extending above the isolation structure.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: October 25, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Jody A. Fronheiser, Yi Qi, Sylvie Mignot
  • Uniaxially-strained FD-SOI finFET
    Patent number: 9466664
    Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: October 11, 2016
    Assignees: STMICROELECTRONICS, INC., COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, GLOBALFOUNDRIES INC.
    Inventors: Pierre Morin, Maud Vinet, Laurent Grenouillet, Ajey Poovannummoottil Jacob
  • Methods of forming doped epitaxial SiGe material on semiconductor devices
    Patent number: 9455140
    Abstract: One illustrative method disclosed herein includes, among other things, performing first and second in situ doping, epitaxial deposition processes to form first and second layers of in situ doped epi semiconductor material, respectively, above a semiconductor substrate, wherein one of the first and second layers has a high level of germanium and a low level of P-type dopant material and the other of the first and second layers has a low level of germanium and a high level of P-type dopant material, and performing a mixing thermal anneal process on the first and second layers so as to form the final silicon germanium material having a high level of germanium and a high level of P-type dopant material.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: September 27, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Jody A. Fronheiser, Murat Kerem Akarvardar
  • Methods of forming strained and relaxed germanium fins for PMOS and NMOS finFET devices, respectively
    Patent number: 9455199
    Abstract: One illustrative method disclosed herein includes, among other things, forming a first fin for the PMOS device and a second fin for the NMOS device, wherein each of the first and second fins comprises a lower substrate fin portion and an upper fin portion that is made of semiconductor material that is different from that of the substrate, performing at least one process operation to form a first channel semiconductor material for the PMOS FinFET device that comprises a fully-strained, substantially defect-free substantially pure germanium material on a recessed upper surface of the upper fin portion of the first fin and form a second channel semiconductor material for the NMOS FinFET device that comprises a fully-relaxed substantially pure germanium material that is substantially defect free positioned above an upper surface of the lower substrate fin portion of the second fin.
    Type: Grant
    Filed: February 16, 2016
    Date of Patent: September 27, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Ajey Poovannummoottil Jacob
  • COMMON FABRICATION OF MULTIPLE FINFETs WITH DIFFERENT CHANNEL HEIGHTS
    Publication number: 20160268400
    Abstract: Commonly fabricated FinFET type semiconductor devices with different (i.e., both taller and shorter) heights of an entirety of or only the channel region of some of the fins. Where only the channel of some of the fins has a different height, the sources and drains have a common height higher than those channels. The different fin heights are created by recessing some of the fins, and where only the channels have different heights, the difference is created by exposing a top surface of each channel intended to be shorter, the other channels being masked, and partially recessing the exposed channel(s). In both cases, the mask(s) may then be removed and conventional FinFET processing may proceed.
    Type: Application
    Filed: March 12, 2015
    Publication date: September 15, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Murat Kerem AKARVARDAR, Jody A. FRONHEISER, Ajey Poovannummoottil JACOB
  • FIN ISOLATION STRUCTURES FACILITATING DIFFERENT FIN ISOLATION SCHEMES
    Publication number: 20160260742
    Abstract: Methods and semiconductor structures formed from the methods are provided which facilitate fabricating semiconductor fin structures. The methods include, for example: providing a wafer with at least one semiconductor fin extending above a substrate; transforming a portion of the semiconductor fin(s) into an isolation layer, the isolation layer separating a semiconductor layer of the semiconductor fin(s) from the substrate; and proceeding with forming a fin device(s) of a first architectural type in a first fin region of the semiconductor fin(s), and a fin device(s) of a second architectural type in a second fin region of the semiconductor fin(s), where the first architectural type and the second architectural type are different fin device architectures.
    Type: Application
    Filed: May 17, 2016
    Publication date: September 8, 2016
    Applicants: GLOBALFOUNDRIES Inc., STMICROELECTRONICS, INC.
    Inventors: Ajey Poovannummoottil JACOB, Kangguo CHENG, Bruce DORIS, Nicolas LOUBET, Prasanna KHARE, Rama DIVAKARUNI
  • CONTROLLED JUNCTION TRANSISTORS AND METHODS OF FABRICATION
    Publication number: 20160254361
    Abstract: Embodiments of the present invention provide transistors with controlled junctions and methods of fabrication. A dummy spacer is used during the majority of front end of line (FEOL) processing. Towards the end of the FEOL processing, the dummy spacers are removed and replaced with a final spacer material. Embodiments of the present invention allow the use of a very low-k material, which is highly thermally-sensitive, by depositing it late in the flow. Additionally, the position of the gate with respect to the doped regions is highly controllable, while dopant diffusion is minimized through reduced thermal budgets. This allows the creation of extremely abrupt junctions whose surface position is defined using a sacrificial spacer. This spacer is then removed prior to final gate deposition, allowing a fixed gate overlap that is defined by the spacer thickness and any diffusion of the dopant species.
    Type: Application
    Filed: May 13, 2016
    Publication date: September 1, 2016
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Steven J. Bentley, Ajey Poovannummoottil Jacob, Chia-Yu Chen, Tenko Yamashita
  • METHODS OF MODULATING STRAIN IN PFET AND NFET FINFET SEMICONDUCTOR DEVICES
    Publication number: 20160254195
    Abstract: One illustrative method disclosed herein includes, among other things, forming a plurality of initial fins that have the same initial axial length and the same initial strain above a substrate, performing at least one etching process so as to cut a first fin to a first axial length and to cut a second fin to a second axial length that is less than the first axial length, wherein the cut first fin retains a first amount of the initial strain and the cut second fin retains about zero of the initial strain or a second amount of the initial strain that is less than the first amount, and forming gate structures around the first and second cut fins to form FinFET devices.
    Type: Application
    Filed: February 27, 2015
    Publication date: September 1, 2016
    Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar, Bruce Doris, Ali Khakifirooz
  • Methods of forming fin isolation regions on FinFET semiconductor devices using an oxidation-blocking layer of material and by performing a fin-trimming process
    Patent number: 9431306
    Abstract: A method includes forming a plurality of trenches to define a fin, forming a first layer of insulating material in the trenches, forming a sidewall spacer on opposite sides of the fin above an upper surface of the first layer, removing the first layer and performing a fin-trimming etching process to define a plurality of increased-size trenches. The method also includes forming a first oxidation-blocking layer of insulating material in the increased-size trenches, forming a second layer of insulating material above the oxidation-blocking layer, and performing a thermal anneal process to convert at least a part of the portion of the fin that is in contact with the second layer of insulating material into an oxide fin isolation region.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: August 30, 2016
    Assignees: GLOBALFOUNDRIES Inc., International Business Machines Corporation
    Inventors: Ajey Poovannummoottil Jacob, Bruce Doris, Kangguo Cheng, Ali Khakifirooz, Kern Rim
  • Methods of forming alternative channel materials on FinFET semiconductor devices
    Patent number: 9425289
    Abstract: One illustrative method disclosed herein includes forming a recessed fin structure and a replacement fin cavity in a layer of insulating material above the recessed fin structure, forming at least first and second individual layers of epi semiconductor material in the replacement fin cavity, wherein each of the first and second layers have different concentrations of germanium, performing an anneal process on the first and second layers so as to form a substantially homogeneous SiGe replacement fin in the fin cavity, and forming a gate structure around at least a portion of the replacement fin.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: August 23, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar
  • FinFET semiconductor device with isolated fins made of alternative channel materials
    Patent number: 9425315
    Abstract: One illustrative method disclosed herein includes, among other things, oxidizing a lower portion of an initial fin structure to thereby define an isolation region that vertically separates an upper portion of the initial fin structure from a semiconducting substrate, performing a recess etching process to remove a portion of the upper portion of the initial fin structure so as to define a recessed fin portion, forming a replacement fin on the recessed fin portion so as to define a final fin structure comprised of the replacement fin and the recessed fin portion, and forming a gate structure around at least a portion of the replacement fin.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: August 23, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ajey Poovannummoottil Jacob, Murat Kerem Akarvardar
  • FOLDED BALLISTIC CONDUCTOR INTERCONNECT LINE
    Publication number: 20160225719
    Abstract: A method includes forming a folding template in a first dielectric layer. The folding template has a plurality of surfaces that are positioned in different planes. A ballistic conductor line is formed on the plurality of surfaces of the folding template. A device includes a first dielectric layer and a vertically folded line disposed in the first dielectric layer, the vertically folded line including a ballistic conductor material.
    Type: Application
    Filed: January 29, 2015
    Publication date: August 4, 2016
    Inventor: Ajey Poovannummoottil Jacob
  • SOLID-STATE SUPERCAPACITOR
    Publication number: 20160225542
    Abstract: Embodiments of the present disclosure relate to a solid-state supercapacitor. The solid-state supercapacitor includes a first electrode, a second electrode, and a solid-state ionogel structure between the first electrode and the second electrode. The solid-state ionogel structure prevents direct electrical contact between the first electrode and the second electrode. Further, the solid-state ionogel structure substantially fills voids inside the first electrode and the second electrode.
    Type: Application
    Filed: November 13, 2014
    Publication date: August 4, 2016
    Applicant: INTEL CORPORATION
    Inventors: Bruce S. Dunn, Chi On Chui, Ajey Poovannummoottil Jacob, Daniel Membreno, Leland Smith
  • METHODS OF FORMING FIN ISOLATION REGIONS ON FINFET SEMICONDUCTOR DEVICES USING AN OXIDATION-BLOCKING LAYER OF MATERIAL AND BY PERFORMING A FIN-TRIMMING PROCESS
    Publication number: 20160225677
    Abstract: A method includes forming a plurality of trenches to define a fin, forming a first layer of insulating material in the trenches, forming a sidewall spacer on opposite sides of the fin above an upper surface of the first layer, removing the first layer and performing a fin-trimming etching process to define a plurality of increased-size trenches.
    Type: Application
    Filed: March 21, 2016
    Publication date: August 4, 2016
    Inventors: Ajey Poovannummoottil Jacob, Bruce Doris, Kangguo Cheng, Ali Khakifirooz, Kern Rim