Abstract: An interconnection layer carrying structure for transferring an interconnection layer onto a substrate is disclosed. The interconnection layer carrying structure includes a support substrate, a release layer on the support substrate; and an interconnection layer on the release layer. The interconnection layer includes an organic insulating material and a set of pads embedded in the organic insulating material. The set of the pads is configured to face towards the support substrate. The support substrate has a base part where the interconnection layer is formed and an extended part extending outside the base part.

Abstract: A device includes a solid-state thin film battery (STFB) configured for use as an energy storage device of a microcomputing device. The STFB includes an anode and a cathode to account for voltage mismatch by enabling a first electromotive force associated with the STFB to be less than a second electromotive force associated with a photovoltaic device of the microcomputing device.

Abstract: An interconnection layer carrying structure for transferring an interconnection layer onto a substrate is disclosed. The interconnection layer carrying structure includes a support substrate, a release layer on the support substrate; and an interconnection layer on the release layer. The interconnection layer includes an organic insulating material and a set of pads embedded in the organic insulating material. The set of the pads is configured to face towards the support substrate. The support substrate has a base part where the interconnection layer is formed and an extended part extending outside the base part.

Abstract: A method for sampling breath gas, includes collecting a first breath sample in a first bag. The first breath sample is an initial part of expired gas expired after inspiration. Additionally, the method includes collecting a second breath sample in a second bag. The second breath sample is a latter part of the expired gas. The method includes subtracting first mass spectral data obtained by mass spectroscopy of the first breath sample collected in the first bag from second mass spectral data obtained by mass spectroscopy of the second breath sample collected in the second bag.

Abstract: A method for fabricating a stacked battery structure. The method includes preparing a plurality of battery layers separately, wherein each battery layer includes a substrate, a film battery element fabricated on the substrate and an insulator formed over the film battery element. The insulator has a flat top surface and the film battery element includes a current collector. The method also includes stacking the plurality of battery layers, wherein the insulator of a first battery layer of the plurality of battery layers bonds to the substrate of a second battery layer of the plurality of battery layers by the flat top surface. The method further includes forming a conductive path within the plurality of battery layers, wherein the conductive path connects with at least one of the current collectors of the plurality of battery layers.

Abstract: A method for fabricating a stacked battery structure. The method includes preparing a plurality of battery layers separately, wherein each battery layer includes a substrate, a film battery element fabricated on the substrate and an insulator formed over the film battery element. The insulator has a flat top surface and the film battery element includes a current collector. The method also includes stacking the plurality of battery layers, wherein the insulator of a first battery layer of the plurality of battery layers bonds to the substrate of a second battery layer of the plurality of battery layers by the flat top surface. The method further includes forming a conductive path within the plurality of battery layers, wherein the conductive path connects with at least one of the current collectors of the plurality of battery layers.

Abstract: A method for fabricating an electron device stack structure includes preparing plural substrates, each having a corresponding one of plural vias; sputter-depositing plural metal layers on the plural substrates to form plural electron device layers, each of the plural metal layers being sputter-deposited on a corresponding one of the plural substrates and including a part straying into a corresponding one of the plural vias as a corresponding one of plural stray metal portions; stacking the plural electron device layers to construct the electron device stack structure having a conductive path formed by connecting the plural vias; and injecting a conductive material into the conductive path to form a vertical electrical connection among the plural stray metal portions.

Abstract: A method for fabricating a stacked device structure includes preparing plural device layers each having a glass layer, a metal layer, and a resin layer. The metal layer corresponds to one of plural metal layers. The method further includes stacking the plural device layers to compose stacked device layers; and drilling vertically a hole into the stacked device layers by laser such that the plural metal layers are exposed to the hole and filling conductive material into the hole to connect the plural metal layers.

Abstract: There is provided a circuit module where a sufficient amount of underfill resin may be supplied to corner portions of a semiconductor chip. A circuit module includes a circuit board provided with a plurality of electrode pads on a surface of the board, a semiconductor chip arranged on the board, the chip including a surface and a back surface, where each of a plurality of solder bumps and provided on the back surface is solder joined to a corresponding one of the plurality of electrode pads, and an underfill provided between the surface of the board and the back surface of the chip. Furthermore, the chip includes an eaves portion of a predetermined thickness at an outer periphery of the surface, and the underfill forms a fillet extending from a bottom surface of the eaves portion to the surface of the board along a side wall of the chip.

Abstract: A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.

Abstract: A method for fabricating an electron device stack structure includes preparing plural substrates, each having a corresponding one of plural vias; sputter-depositing plural metal layers on the plural substrates to form plural electron device layers, each of the plural metal layers being sputter-deposited on a corresponding one of the plural substrates and including a part straying into a corresponding one of the plural vias as a corresponding one of plural stray metal portions; stacking the plural electron device layers to construct the electron device stack structure having a conductive path formed by connecting the plural vias; and injecting a conductive material into the conductive path to form a vertical electrical connection among the plural stray metal portions.

Abstract: A chip pickup system is provided. The chip pickup system includes a detector for detecting a position of an irregular semiconductor chip on a holder. The holder holding plural semiconductor chips in predetermined positions on the holder. The irregular semiconductor chip is out of the predetermined positions. The system further includes a pickup tool for picking up the irregular semiconductor chip at least on the basis of information on the position of the irregular semiconductor chip detected by the detector.

Abstract: A technique for interconnecting chips by using an interconnection substrate is disclosed. The interconnection substrate includes a base substrate, a first group of electrodes on the base substrate for a first chip to be mounted, and a second group of electrodes on the base substrate for a second chip to be mounted. The interconnection substrate further includes an interconnection layer that includes a first set of pads for the first chip, a second set of pads for the second chip, traces and an organic insulating material. The interconnection layer is disposed on the base substrate and located within a defined area on the base substrate between the first group of electrodes and the second group of the electrodes.

Abstract: An interconnection layer carrying structure for transferring an interconnection layer onto a substrate is disclosed. The interconnection layer carrying structure includes a support substrate, a release layer on the support substrate; and an interconnection layer on the release layer. The interconnection layer includes an organic insulating material and a set of pads embedded in the organic insulating material. The set of the pads is configured to face towards the support substrate. The support substrate has a base part where the interconnection layer is formed and an extended part extending outside the base part.

Abstract: A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.

Abstract: A technique for interconnecting chips by using an interconnection substrate is disclosed. The interconnection substrate includes a base substrate, a first group of electrodes on the base substrate for a first chip to be mounted, and a second group of electrodes on the base substrate for a second chip to be mounted. The interconnection substrate further includes an interconnection layer that includes a first set of pads for the first chip, a second set of pads for the second chip, traces and an organic insulating material. The interconnection layer is disposed on the base substrate and located within a defined area on the base substrate between the first group of electrodes and the second group of the electrodes.

Abstract: Methods of bonding chips to a substrate and transfer wafers used for such bonding include bonding chips to a first support wafer by a first adhesive layer. The chips are bonded to a second support wafer by a second adhesive layer. Regions of the first adhesive layer are selectively weakened to decrease an adhesive strength in weakened regions. The weakened regions correspond to a subset of chips. The second support wafer is separated from the first wafer, such that the subset of chips in the weakened regions debond from the first support wafer. The subset of chips are bonded to a target substrate.

Abstract: A method for fabricating a stacked battery structure. The method includes preparing a plurality of battery layers separately, wherein each battery layer includes a substrate, a film battery element fabricated on the substrate and an insulator formed over the film battery element. The insulator has a flat top surface and the film battery element includes a current collector. The method also includes stacking the plurality of battery layers, wherein the insulator of a first battery layer of the plurality of battery layers bonds to the substrate of a second battery layer of the plurality of battery layers by the flat top surface. The method further includes forming a conductive path within the plurality of battery layers, wherein the conductive path connects with at least one of the current collectors of the plurality of battery layers.

Abstract: A method for fabricating a stacked battery structure. The method includes preparing a plurality of battery layers separately, wherein each battery layer includes a substrate, a film battery element fabricated on the substrate and an insulator formed over the film battery element. The insulator has a flat top surface and the film battery element includes a current collector. The method also includes stacking the plurality of battery layers, wherein the insulator of a first battery layer of the plurality of battery layers bonds to the substrate of a second battery layer of the plurality of battery layers by the flat top surface. The method further includes forming a conductive path within the plurality of battery layers, wherein the conductive path connects with at least one of the current collectors of the plurality of battery layers.

Abstract: A method for fabricating a stacked battery structure. The method includes preparing a plurality of battery layers separately, wherein each battery layer includes a substrate, a film battery element fabricated on the substrate and an insulator formed over the film battery element. The insulator has a flat top surface and the film battery element includes a current collector. The method also includes stacking the plurality of battery layers, wherein the insulator of a first battery layer of the plurality of battery layers bonds to the substrate of a second battery layer of the plurality of battery layers by the flat top surface. The method further includes forming a conductive path within the plurality of battery layers, wherein the conductive path connects with at least one of the current collectors of the plurality of battery layers.