Patents by Inventor Akihiro Horibe
Akihiro Horibe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10424510Abstract: A method for filling a through hole with solder includes mounting a substrate having a through hole formed therein on a permeable barrier layer having pores that enable gas to flow through the permeable barrier. A solder source is positioned over the through hole. Molten solder is delivered in the through hole with a positive pressure from the solder source such that gas in the through holes passes the permeable barrier while the molten solder remains in the through hole.Type: GrantFiled: August 7, 2017Date of Patent: September 24, 2019Assignee: International Business Machines CorporationInventors: Toyohiro Aoki, Akihiro Horibe, Kuniaki Sueoka, Kazushige Toriyama
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Patent number: 10388578Abstract: A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.Type: GrantFiled: October 27, 2017Date of Patent: August 20, 2019Assignee: International Business Machines CorporationInventors: Akihiro Horibe, Yasuteru Kohda, Seiji Munetoh, Chitra Subramanian, Kuniaki Sueoka
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Patent number: 10388566Abstract: A method for filling a through hole with solder includes mounting a substrate having a through hole formed therein on a permeable barrier layer having pores that enable gas to flow through the permeable barrier. A solder source is positioned over the through hole. Molten solder is delivered in the through hole with a positive pressure from the solder source such that gas in the through holes passes the permeable barrier while the molten solder remains in the through hole.Type: GrantFiled: March 11, 2016Date of Patent: August 20, 2019Assignee: International Business Machines CorporationInventors: Toyohiro Aoki, Akihiro Horibe, Kuniaki Sueoka, Kazushige Toriyama
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Publication number: 20190214339Abstract: Methods for fabricating a via structure are disclosed. In one method, fabricating the via structure includes disposing a stress buffer layer on a first surface of a substrate. The stress buffer layer has an opening aligned to a via hole of the substrate. The method further includes filling the via hole with a conductive material at least up to the first surface of the substrate. The stress buffer layer reduces stress generated due to coefficient of thermal expansion mismatch associated with the via hole and the substrate, and the conductive material extends into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface of the substrate around the via hole.Type: ApplicationFiled: March 14, 2019Publication date: July 11, 2019Inventors: Toyohiro Aoki, Takashi Hisada, Akihiro Horibe, Sayuri Hada, Eiji I. Nakamura, Kuniaki Sueoka
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Patent number: 10325839Abstract: A via structure for electric connection is disclosed. The via structure includes a substrate that has a first surface and a via hole opened to the first surface. The via structure includes also a stress buffer layer disposed on the first surface of the substrate, which has an opening aligned to the via hole of the substrate. The via structure further includes a conductive body formed in the via hole of the substrate at least up to the level of the first surface of the substrate. In the via structure, the stress buffer layer receives the conductive body extending into the opening over the level of the first surface of the substrate and/or covers, at least in part, the edge of the first surface around the via hole of the substrate.Type: GrantFiled: April 6, 2017Date of Patent: June 18, 2019Assignee: International Business Machines CorporationInventors: Toyohiro Aoki, Takashi Hisada, Akihiro Horibe, Sayuri Hada, Eiji I. Nakamura, Kuniaki Sueoka
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Patent number: 10317625Abstract: A method of fabricating a polymer waveguide (PWG) is presented. The method includes preparing a polymer waveguide (PWG) sheet having a surface with partially exposed cores and partially exposed cladding, the cladding covering the cores and preparing a first dicing tape, the first dicing tape being an ultraviolet (UV) cut type dicing tape defining separation lines on a back side thereof. The method further includes placing the partially exposed cores of the PWG sheet on the first dicing tape to prevent the surface of the PWG sheet from atmospheric contaminations and placing a tape side of the first dicing tape attached to the PWG sheet on a second dicing tape.Type: GrantFiled: August 20, 2018Date of Patent: June 11, 2019Assignee: International Business Machines CorporationInventors: Akihiro Horibe, Hidetoshi Numata
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Polymer waveguide connector assembly method using cores and cladding that are both partially exposed
Patent number: 10302868Abstract: A method of fabricating a polymer waveguide (PWG) is presented. The method includes preparing a polymer waveguide (PWG) sheet having a surface with partially exposed cores and partially exposed cladding, the cladding covering the cores and preparing a first dicing tape, the first dicing tape being an ultraviolet (UV) cut type dicing tape defining separation lines on a back side thereof. The method further includes placing the partially exposed cores of the PWG sheet on the first dicing tape to prevent the surface of the PWG sheet from atmospheric contaminations and placing a tape side of the first dicing tape attached to the PWG sheet on a second dicing tape.Type: GrantFiled: August 20, 2018Date of Patent: May 28, 2019Assignee: International Business Machines CorporationInventors: Akihiro Horibe, Hidetoshi Numata -
Publication number: 20190139840Abstract: A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.Type: ApplicationFiled: December 28, 2018Publication date: May 9, 2019Inventors: Akihiro Horibe, Yasuteru Kohda, Seiji Munetoh, Chitra Subramanian, Kuniaki Sueoka
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Patent number: 10252363Abstract: Forming a solder joint between metal layers by preparing a structure having solder material placed between two metal layers and heating the structure to grow an intermetallic compound in a space between the two metal layers. Growing the intermetallic compound includes setting a first surface, in contact with the solder material between the two metal layers, to a first temperature, thereby enabling growth of the intermetallic compound; setting a second surface, in contact with the solder material between the two metal layers, to a second temperature, wherein the second temperature is higher than the first temperature; and maintaining a temperature gradient (temperature/unit thickness) between the two metal layers at a predetermined value or higher until the intermetallic compound substantially fills the space between the two metal layers.Type: GrantFiled: January 10, 2017Date of Patent: April 9, 2019Assignee: International Business Machines CorporationInventors: Toyohiro Aoki, Akihiro Horibe, Hiroyuki Mori, Yasumitsu Orii, Kazushige Toriyama, Ting-Li Yang
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Publication number: 20190103327Abstract: A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.Type: ApplicationFiled: October 2, 2017Publication date: April 4, 2019Inventors: Akihiro Horibe, Yasuteru Kohda, Seiji Munetoh, Chitra Subramanian, Kuniaki Sueoka
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Publication number: 20190103328Abstract: A chip intermediate body includes a semiconductor region including plural chip areas. The chip areas respectively are cut out as semiconductor chips. A cut region is provided along edges of the chip areas, the cut region being cut to cut out the semiconductor chips. A contact region is provided opposite to the chip areas across the cut region, the contact region being configured to be contacted by a probe of a test unit to test the chip areas, and electric wiring is provided continuously with the cut region to connect the chip areas and the contact region.Type: ApplicationFiled: October 27, 2017Publication date: April 4, 2019Inventors: Akihiro Horibe, Yasuteru Kohda, Seiji Munetoh, Chitra Subramanian, Kuniaki Sueoka
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Publication number: 20190072722Abstract: A method of fabricating a polymer waveguide (PWG) is presented. The method includes preparing a polymer waveguide (PWG) sheet having a surface with partially exposed cores and partially exposed cladding, the cladding covering the cores and preparing a first dicing tape, the first dicing tape being an ultraviolet (UV) cut type dicing tape defining separation lines on a back side thereof. The method further includes placing the partially exposed cores of the PWG sheet on the first dicing tape to prevent the surface of the PWG sheet from atmospheric contaminations and placing a tape side of the first dicing tape attached to the PWG sheet on a second dicing tape.Type: ApplicationFiled: August 20, 2018Publication date: March 7, 2019Inventors: Akihiro Horibe, Hidetoshi Numata
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Publication number: 20190072721Abstract: A method of fabricating a polymer waveguide (PWG) is presented. The method includes preparing a polymer waveguide (PWG) sheet having a surface with partially exposed cores and partially exposed cladding, the cladding covering the cores and preparing a first dicing tape, the first dicing tape being an ultraviolet (UV) cut type dicing tape defining separation lines on a back side thereof. The method further includes placing the partially exposed cores of the PWG sheet on the first dicing tape to prevent the surface of the PWG sheet from atmospheric contaminations and placing a tape side of the first dicing tape attached to the PWG sheet on a second dicing tape.Type: ApplicationFiled: August 20, 2018Publication date: March 7, 2019Inventors: Akihiro Horibe, Hidetoshi Numata
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Publication number: 20190051605Abstract: A technique for interconnecting chips by using an interconnection substrate is disclosed. The interconnection substrate includes a base substrate, a first group of electrodes on the base substrate for a first chip to be mounted, and a second group of electrodes on the base substrate for a second chip to be mounted. The interconnection substrate further includes an interconnection layer that includes a first set of pads for the first chip, a second set of pads for the second chip, traces and an organic insulating material. The interconnection layer is disposed on the base substrate and located within a defined area on the base substrate between the first group of electrodes and the second group of the electrodes.Type: ApplicationFiled: November 6, 2017Publication date: February 14, 2019Inventors: Akihiro Horibe, Hiroyuki Mori, Keishi Okamoto
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Publication number: 20190051943Abstract: A technique relating to a battery structure is disclosed. A base substrate and a battery layer having a support substrate are prepared. The battery layer includes a protection layer formed on the support substrate, a film battery element formed on the protection layer and an insulator covering the film battery element. The battery layer is placed onto the base substrate with the bottom of the support substrate facing up. The support substrate is then removed from the battery layer at least in part by etching while protecting the film battery element by the protection layer. A stacked battery structure including the base substrate and the two or more battery layers is also disclosed.Type: ApplicationFiled: August 10, 2017Publication date: February 14, 2019Inventors: Akihiro Horibe, Kuniaki Sueoka, Takahito Watanabe
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Publication number: 20190051944Abstract: A technique relating to a battery structure is disclosed. A base substrate and a battery layer having a support substrate are prepared. The battery layer includes a protection layer formed on the support substrate, a film battery element formed on the protection layer and an insulator covering the film battery element. The battery layer is placed onto the base substrate with the bottom of the support substrate facing up. The support substrate is then removed from the battery layer at least in part by etching while protecting the film battery element by the protection layer. A stacked battery structure including the base substrate and the two or more battery layers is also disclosed.Type: ApplicationFiled: November 13, 2017Publication date: February 14, 2019Inventors: Akihiro Horibe, Kuniaki Sueoka, Takahito Watanabe
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Publication number: 20190051603Abstract: A technique for interconnecting chips by using an interconnection substrate is disclosed. The interconnection substrate includes a base substrate, a first group of electrodes on the base substrate for a first chip to be mounted, and a second group of electrodes on the base substrate for a second chip to be mounted. The interconnection substrate further includes an interconnection layer that includes a first set of pads for the first chip, a second set of pads for the second chip, traces and an organic insulating material. The interconnection layer is disposed on the base substrate and located within a defined area on the base substrate between the first group of electrodes and the second group of the electrodes.Type: ApplicationFiled: August 10, 2017Publication date: February 14, 2019Inventors: Akihiro Horibe, Hiroyuki Mori, Keishi Okamoto
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Patent number: 10170443Abstract: A debonding device includes a first member provided with a recess for receiving a carrier body, the carrier body including a first plate, a second plate, and plural semiconductor chips. The semiconductor chips are sandwiched between the first plate and the second plate, the first plate of the carrier body received in the recess being opposed to a bottom of the recess. A second member is configured to change a relative position with respect to the first member, wherein the second member holds the second plate of the carrier body received in the recess using a vacuum suction, and the first member is provided with an inlet to introduce gas into a gap between the first plate and the second plate of the carrier body received in the recess.Type: GrantFiled: November 28, 2017Date of Patent: January 1, 2019Assignee: International Business Machines CorporationInventor: Akihiro Horibe
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Publication number: 20180366388Abstract: There is provided a circuit module where a sufficient amount of underfill resin may be supplied to corner portions of a semiconductor chip. A circuit module includes a circuit board provided with a plurality of electrode pads on a surface of the board, a semiconductor chip arranged on the board, the chip including a surface and a back surface, where each of a plurality of solder bumps and provided on the back surface is solder joined to a corresponding one of the plurality of electrode pads, and an underfill provided between the surface of the board and the back surface of the chip. Furthermore, the chip includes an eaves portion of a predetermined thickness at an outer periphery of the surface, and the underfill forms a fillet extending from a bottom surface of the eaves portion to the surface of the board along a side wall of the chip.Type: ApplicationFiled: August 23, 2018Publication date: December 20, 2018Applicant: International Business Machines CorporationInventors: Akihiro HORIBE, Sayuri HADA, Kuniaki SUEOKA
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Patent number: 10141278Abstract: Highly reliable chip mounting is accomplished by using a substrate having such a shape that a stress exerted on a flip-chip-connected chip can be reduced, so that the stress exerted on the chip is reduced and separation of an interlayer insulating layer having a low dielectric constant (low-k) is minimized. Specifically, in a chip mounting structure, a chip including an interlayer insulating layer having a low dielectric constant (low-k) is flip-chip connected to a substrate via bumps is shown. In the chip mounting structure, the substrate has such a shape that a mechanical stress exerted on the interlayer insulating layer at corner portions of the chip due to a thermal stress is reduced, the thermal stress occurring due to a difference in coefficient of thermal expansion between the chip and the substrate.Type: GrantFiled: November 6, 2017Date of Patent: November 27, 2018Assignee: International Business Machines CorporationInventors: Akihiro Horibe, Keiji Matsumoto, Keishi Okamoto, Kazushige Toriyama