Abstract: A semiconductor structure including a through electrode includes a lamination body including at least three layers, including respective vertically aligned electrode parts, the electrode part on the surface of an uppermost layer and including an aperture, the electrode part of the intermediate layer having an aperture smaller than the aperture of the uppermost layer; a through-hole extending from the aperture of the electrode part on the uppermost layer to the surface of the electrode part on a lowermost layer, the through-hole having a depressed part on a side wall thereof between the electrode parts therein; an insulating layer disposed on the entire side wall in the through-hole at a part other than on surfaces of the electrode parts; and a conductive material filling the through-hole from the surface of the electrode part on the lowermost layer to the surface of the electrode part on the uppermost layer.

Abstract: A semiconductor structure including a through electrode includes a lamination body including at least three layers, including respective vertically aligned electrode parts, the electrode part on the surface of an uppermost layer and including an aperture, the electrode part of the intermediate layer having an aperture smaller than the aperture of the uppermost layer; a through-hole extending from the aperture of the electrode part on the uppermost layer to the surface of the electrode part on a lowermost layer, the through-hole having a depressed part on a side wall thereof between the electrode parts therein; an insulating layer disposed on the entire side wall in the through-hole at a part other than on surfaces of the electrode parts; and a conductive material filling the through-hole from the surface of the electrode part on the lowermost layer to the surface of the electrode part on the uppermost layer.

Abstract: There is provided a circuit module where a sufficient amount of underfill resin may be supplied to corner portions of a semiconductor chip. A circuit module includes a circuit board provided with a plurality of electrode pads on a surface of the board, a semiconductor chip arranged on the board, the chip including a surface and a back surface, where each of a plurality of solder bumps and provided on the back surface is solder joined to a corresponding one of the plurality of electrode pads, and an underfill provided between the surface of the board and the back surface of the chip. Furthermore, the chip includes an eaves portion of a predetermined thickness at an outer periphery of the surface, and the underfill forms a fillet extending from a bottom surface of the eaves portion to the surface of the board along a side wall of the chip.

Abstract: A semiconductor structure including a through electrode includes a lamination body including at least three layers, including respective vertically aligned electrode parts, the electrode part on the surface of an uppermost layer and including an aperture, the electrode part of the intermediate layer having an aperture smaller than the aperture of the uppermost layer; a through-hole extending from the aperture of the electrode part on the uppermost layer to the surface of the electrode part on a lowermost layer, the through-hole having a depressed part on a side wall thereof between the electrode parts therein; an insulating layer disposed on the entire side wall in the through-hole at a part other than on surfaces of the electrode parts; and a conductive material filling the through-hole from the surface of the electrode part on the lowermost layer to the surface of the electrode part on the uppermost layer.

Abstract: Forming a solder joint between metal layers by preparing a structure having solder material placed between two metal layers and heating the structure to grow an intermetallic compound in a space between the two metal layers. Growing the intermetallic compound includes setting a first surface, in contact with the solder material between the two metal layers, to a first temperature, thereby enabling growth of the intermetallic compound; setting a second surface, in contact with the solder material between the two metal layers, to a second temperature, wherein the second temperature is higher than the first temperature; and maintaining a temperature gradient (temperature/unit thickness) between the two metal layers at a predetermined value or higher until the intermetallic compound substantially fills the space between the two metal layers.

Abstract: A semiconductor structure including a through electrode includes a lamination body including at least three layers, including respective vertically aligned electrode parts, the electrode part on the surface of an uppermost layer and including an aperture, the electrode part of the intermediate layer having an aperture smaller than the aperture of the uppermost layer; a through-hole extending from the aperture of the electrode part on the uppermost layer to the surface of the electrode part on a lowermost layer, the through-hole having a depressed part on a side wall thereof between the electrode parts therein; an insulating layer disposed on the entire side wall in the through-hole at a part other than on surfaces of the electrode parts; and a conductive material filling the through-hole from the surface of the electrode part on the lowermost layer to the surface of the electrode part on the uppermost layer.

Abstract: To reduce the risk of reduction in yield due to breakage of a thin wafer or a thin chip having through silicon vias (TSVs) formed therein in a chip bonding process, and to prevent warping during handling of a chip-on-wafer (CoW). Chips are bonded to a wafer having TSVs formed therein and sealed before the wafer is thinned. Subsequently, the CoW is subjected to a process of thinning the TSV wafer, a back-surface treatment, and a process of cutting the wafer into small pieces by dicing. Although thin wafers and thin chips having TSVs formed therein are difficult to handle since the chips are bonded to the wafer before thinning and the wafer is thinned and cut into small pieces while mechanical strength thereof is increased by fixing a support to the wafer, the yield of three-dimensional stacked devices can be increased.

Abstract: To reduce the risk of reduction in yield due to breakage of a thin wafer or a thin chip having through silicon vias (TSVs) formed therein in a chip bonding process, and to prevent warping during handling of a chip-on-wafer (CoW). Chips are bonded to a wafer having TSVs formed therein and sealed before the wafer is thinned. Subsequently, the CoW is subjected to a process of thinning the TSV wafer, a back-surface treatment, and a process of cutting the wafer into small pieces by dicing. Although thin wafers and thin chips having TSVs formed therein are difficult to handle since the chips are bonded to the wafer before thinning and the wafer is thinned and cut into small pieces while mechanical strength thereof is increased by fixing a support to the wafer, the yield of three-dimensional stacked devices can be increased.

Abstract: To reduce the risk of reduction in yield due to breakage of a thin wafer or a thin chip having through silicon vias (TSVs) formed therein in a chip bonding process, and to prevent warping during handling of a chip-on-wafer (CoW). Chips are bonded to a wafer having TSVs formed therein and sealed before the wafer is thinned. Subsequently, the CoW is subjected to a process of thinning the TSV wafer, a back-surface treatment, and a process of cutting the wafer into small pieces by dicing. Although thin wafers and thin chips having TSVs formed therein are difficult to handle since the chips are bonded to the wafer before thinning and the wafer is thinned and cut into small pieces while mechanical strength thereof is increased by fixing a support to the wafer, the yield of three-dimensional stacked devices can be increased.

Abstract: The present invention includes the following steps: setting the thickness of an interposer to an initial value; determining the axial force of the interposer and the radius of curvature of the warpage caused by the difference in the thermal expansion coefficients of the supporting substrate, the joined layer and the interposer at the set thickness; determining the absolute value of the stress on the chip-connecting surface of the interposer from the stress due to the axial force of the interposer and the stress due to the warpage using the determined axial force and the radius of curvature; determining whether or not the absolute value of the stress is within a tolerance; changing the thickness of the interposer by a predetermined value; and confirming the set thickness as the thickness of the interposer when the determined absolute value of the stress is within the tolerance.

Abstract: A method and apparatus to detect a defect in a three-dimensional integrated structure by ultrasound scanning and to non-destructively detect the presence of a void that can occur in a process in a through silicon via (TSV) arranged in a board, such as a silicon wafer. To avoid measurement by ultrasound scanning over a board surface from being impeded by an object, such as a (solder) bump, scattering ultrasound, one or more TSVs belonging to a test element group (TEG) are selected from among a plurality of TSVs such that physical obstruction in the vicinity of the TEG.

Abstract: The present invention relates to a method of multi chip stack bonding. A resin mixture is applied to a chip wafer and the chip wafer is heated until the resin mixture has solidified. The chip wafer is fragmented into individual chips and the individual chips are pre-stacked with alignment into a multi-chip stack in a joining process. Pressure and heating is applied to the multi-chip stack until the joining process is completed.

Abstract: The present invention relates to a method of aligning circular multi-core fibers, wherein the method utilized independent and individually selected cores to receive, transmit, and emit light from input devices. The present invention further relates to positioning the ends of a multi-core fiber in order to detect and determine the precise locations of individually selected core fibers.

Abstract: A lighting system includes a light guide plate, having a plane of incidence into which light enters and a plane of emission from which the light is emitted, a light source, having a luminous portion and a non-luminous portion, that is located adjacent to the light guide plate so that the light guide plate is irradiated by light. The system further includes a lamp socket, for holding at least one end of the light source, and a reflector, which is extended along the light source for reflecting the light produced by the light source. The lamp socket exhibits a transmittance of 20 to 90% in wavelengths of from 300 to 900 nm, and the light is scattered through the lamp socket. An embodiment discloses also relates to a display device using the above described side light device.

Abstract: A lighting system includes a light guide plate, having a plane of incidence into which light enters and a plane of emission from which the light is emitted, a light source, having a luminous portion and a non-luminous portion, that is located adjacent to the light guide plate so that the light guide plate is irradiated by light. The system further includes a lamp socket, for holding at least one end of the light source, and a reflector, which is extended along the light source for reflecting the light produced by the light source. The lamp socket exhibits a transmittance of 20 to 90% in wavelengths of from 300 to 900 nm, and the light is scattered through the lamp socket. An embodiment discloses also relates to a display device using the above described side light device.

Abstract: A color liquid crystal display device is disclosed which is capable of securing sufficient luminance while achieving a high National Television System Committee (NTSC) ratio. Specifically, a liquid crystal display device is disclosed which includes a cold cathode fluorescent light tube as a light source, and a liquid crystal display panel for displaying images by controlling transmission of light from the cold cathode fluorescent light tube. The liquid crystal display panel includes a color filter substrate having color filter layers of red, green and blue, a thin film transistor (TFT) array substrate, and a liquid crystal material filled between the TFT array substrate and the color filter substrate. The cold cathode fluorescent light tube is a tri-phospher fluorescent fluorescent light tube, which utilizes Zn2SiO4:Mn as a green phosphor.

Abstract: A color liquid crystal display device is disclosed which is capable of securing sufficient luminance while achieving a high National Television System Committee (NTSC) ratio. Specifically, a liquid crystal display device is disclosed which includes a cold cathode fluorescent light tube as a light source, and a liquid crystal display panel for displaying images by controlling transmission of light from the cold cathode fluorescent light tube. The liquid crystal display panel includes a color filter substrate having color filter layers of red, green and blue, a thin film transistor (TFT) array substrate, and a liquid crystal material filled between the TFT array substrate and the color filter substrate. The cold cathode fluorescent light tube is a tri-phospher fluorescent fluorescent light tube, which utilizes Zn2SiO4:Mn as a green phosphor.

Abstract: A set of light guide blocks B L 1˜B L 3 provide a tandem arrangement. The light guide block B L 1 is supplied with light from a primary light source L 1. The other primary light sources L 2, L 3 are arranged in recesses formed around distal portions of the light guide blocks B L 1, B L 2, supplying the light guide blocks B L 2, B L 3 with primary light, respectively. Overlap of mutually neighboring light guide blocks gives tang-shaped overlapping portions 17a, 17b, 27a, 27b as well as overlapping bands 17c, 27c, thereby avoiding electrodes at both ends of the primary light sources L 2, L 3 from causing short of brightness. The light guide blocks B L 1˜B L 3 may be in the form of unified single guide plate. Primary light sources L 1˜L 3 may have a shape such that electrode sections of both ends are curved. A compact surface light source device with a large emission area is provided.

Abstract: A light source device outputs illumination light with highly uniform tint. The light source device is comprises a scattering guide provided with scattering power inside, a light supplier to supply light to an end face portion of the scattering guide. Light is introduced into the scattering guide plate to be followed by emission from an emission face of the scattering guide. Scattering efficiency is intentionally balanced in a long wavelength region and in a short wavelength region so that regions near the end face and far from the end face are approximately equal in color temperature of output light. Relation between Q(R), efficiency in a long wavelength region, and Q(B), scattering efficiency in a short wavelength region, are designed so that k=Q(B)/Q(R) falls within a range 0.75≦k≦1.25.