Patents by Inventor Akio Nakamura

Akio Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20030038361
    Abstract: A semiconductor apparatus includes a semiconductor pellet having electrodes thereon; a plurality of lead terminals, which electrically connect the electrodes of the semiconductor pellet to terminals formed on a substrate; and a molding member, which is filled around the semiconductor pellet and upper parts of the lead terminals. The plurality of lead terminals are shaped to be elongated strips and are arranged to extend out of the molding member toward the substrate.
    Type: Application
    Filed: August 6, 2002
    Publication date: February 27, 2003
    Inventor: Akio Nakamura
  • Publication number: 20020196040
    Abstract: A device carrier capable of reliably measuring electric characteristics of the device with accuracy and an auto-handle are provided. The device carrier holds an IC having terminals on a lower face thereof at multiple positions, and allows the terminals to be brought into contact with contacts provided on an IC socket, wherein the device carrier comprises an opening through which the device can pass, a support part disposed on the opening for supporting the lower face of the IC, and a hinge part for turnably supporting the support part, wherein said supporter part is turned to release the support of the device when the socket approaches thereto. The supporter part engages with the release pins as the device carrier approaches to the IC socket to be turned so as to release the support of the lower face of the IC. The IC which has been released from being supported by the supporter part passes through the opening and is placed on the IC socket.
    Type: Application
    Filed: June 12, 2002
    Publication date: December 26, 2002
    Inventors: Osamu Arakawa, Akio Nakamura
  • Patent number: 6476505
    Abstract: A semiconductor pullet 1 includes an integrated circuit formed in the central area of the pellet 1, first electric pads 2 arranged in a line in the peripheral area and second electric pads 3 connected to the conductive lines 4 each of which has a second width L. The first pad 2 has a first width S1 and arranged with a first interval P. The second pads 3 have a third width S2 and are located outside of the first pads 2 in a parallel line to the line of said first pads with a second interval C. The first, second and third widths S1, L, S2 and the first interval P has the relationship P>S2>S1+L. Each of the second pads 3 are located at the positions corresponding to the middle positions between the first pads 2 adjoining each other where the second pads 3 are located in a first area (region A) which is inside of straight lines from a center of the semiconductor pellet having an angle &thgr; with a side of the semiconductor pellet 1, in which &thgr;>tan−1(2C/(P−S1)).
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: November 5, 2002
    Assignee: Oki Electric Industry CO, Ltd.
    Inventor: Akio Nakamura
  • Publication number: 20020158264
    Abstract: A GaAsP-base light emitting element capable of sustaining an excellent light emission property for a long period, and a method for manufacturing thereof are provided. The light emitting element 1 has a p-n junction interface responsible for light emission formed between a p-type GaAs1-aPa layer 9 and an n-type GaAs1-aPa layer 8, and has a nitrogen-doped zone 8c formed in a portion including the p-n junction interface between such p-type GaAs1-aPa layer 9 and n-type GaAs1-aPa layer 8. Such element can be manufactured by fabricating a plurality of light emitting elements by varying nitrogen concentration Y of the nitrogen-doped zone 8c while keeping a mixed crystal ratio a of the p-type GaAs1-aPa layer 9 and n-type GaAs1-aPa layer 8 constant; finding an emission luminance/nitrogen concentration relationship by measuring emission luminance of the individual light emitting elements; and adjusting the nitrogen concentration of the nitrogen-doped zone 8c so as to fall within a range from 1.05Yp to 1.
    Type: Application
    Filed: April 25, 2002
    Publication date: October 31, 2002
    Applicant: Shin-Etsu Handotai, Co., Ltd.
    Inventors: Akio Nakamura, Masayuki Shinohara, Masahisa Endo
  • Patent number: 6465913
    Abstract: A power source unit is constructed by an AC/DC switching power source circuit 12, a battery unit 16, switching circuits 13 and 15, detecting circuits 18 and 21 corresponding to the switching circuits 13 and 15, and stop signal forming circuits 19 and 20. In the supplying mode, the power source circuit 12 is made operative, the switching circuit 13 is turned on, an output voltage formed by the power source circuit 12 is supplied to the load side, and at the same time, the switching circuit 15 is turned off by a stop output from the stop signal forming circuit 20. In the charging mode, the power source circuit 12 is made operative, the switching circuit 15 is turned on, the output voltage formed by the power source circuit 12 is supplied to the battery unit 16, and at the same time, the switching circuit 13 is turned off by a stop output of the stop signal forming circuit 19.
    Type: Grant
    Filed: September 27, 2000
    Date of Patent: October 15, 2002
    Assignee: Sony Corporation
    Inventors: Tamiji Nagai, Yoshisada Okayasu, Akio Nakamura, Tsutomu Suda
  • Patent number: 6421807
    Abstract: An apparatus and method for decoding data encoded in a linear cyclic code with less hardware than the prior art decoding apparatus without sacrificing the processing speed are described. The polynomial arithmetic part 14 derives polynomials &sgr;(x), &ohgr;(x) by repeating calculation of the following Qi(x), exchange of polynomials between the register U_reg 180 and the register X_reg 184, and exchange of polynomials between the register Y_reg 182 and the register Z_reg 186 until the degree (deg Xreg) of the polynomial in the register X_reg 184 becomes smaller than [(d−h+1)/2] to solve the following recursive formula.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: July 16, 2002
    Assignee: International Business Machines Corporation
    Inventors: Akio Nakamura, Tetsuya Tamura, Masayuki Demura, Hironobu Nagura
  • Publication number: 20020066964
    Abstract: This invention provides a resin-sealed type semiconductor device capable of decreasing a generation of a simultaneous switching noise even in using a further highly integrated semiconductor LSI. More specifically, this invention provides a resin-type semiconductor device wherein a signal lead frame 105, a power supply lead frame 104 and a grand lead frame 103 are accumulated via an electric insulating layer between layers. The power supply lead frame 104 and the grand lead frame 103 have a mesh shape with a plurality of openings in a plane electric conductor.
    Type: Application
    Filed: September 20, 2001
    Publication date: June 6, 2002
    Inventor: Akio Nakamura
  • Publication number: 20020064900
    Abstract: A semiconductor device comprises a semiconductor IC chip provided with bond pads on its first surface, a wiring board provided with a through hole extending between the opposite surfaces thereof, conductive members electrically connecting the bond pads of the semiconductor IC chip to those formed on the wiring board, and a sealing resin coating coating the surface of the semiconductor IC chip and the conductive members, and bonding the side surfaces of the semiconductor IC chip to the side surfaces of the through hole of the wiring board.
    Type: Application
    Filed: November 9, 2001
    Publication date: May 30, 2002
    Inventor: Akio Nakamura
  • Publication number: 20020043720
    Abstract: A semiconductor device provided with one or more semiconductor pellets arranged on the bottom surface of a recess produced along a surface of a semiconductor plate having wirings arranged on the surface thereof, wirings extending toward the surface of the recess, and the recess being buried with a layer of a resin which is inclined to inflate, while it is hardened, resultantly producing a stress in the resin layer to expand toward the side wall of the recess engraved in the semiconductor plate, resultantly preventing breakage from happening for an interface between the side wall of the recess engraved in the semiconductor plate and the surface of the resin layer contacting the side wall, and remarkably improving the thermal conductivity efficiency to reduce the magnitude of a temperature rise of the semiconductor device, resultantly preventing a delay from happening for the operation speed of the semiconductor device.
    Type: Application
    Filed: December 10, 2001
    Publication date: April 18, 2002
    Inventor: Akio Nakamura
  • Publication number: 20020024149
    Abstract: A semiconductor pullet 1 includes an integrated circuit formed in the central area of the pellet 1, first electric pads 2 arranged in a line in the peripheral area and second electric pads 3 connected to the conductive lines 4 each of which has a second width L. The first pad 2 has a first width S1 and arranged with a first interval P. The second pads 3 have a third width S2 and are located outside of the first pads 2 in a parallel line to the line of said first pads with a second interval C. The first, second and third widths S1, L, S2 and the first interval P has the relationship P>S2>S1+L. Each of the second pads 3 are located at the positions corresponding to the middle positions between the first pads 2 adjoining each other where the second pads 3 are located in a first area (region A) which is inside of straight lines from a center of the semiconductor pellet having an angle &thgr; with a side of the semiconductor pellet 1, in which &thgr;>tan−1(2C/(P−S1)).
    Type: Application
    Filed: August 30, 2001
    Publication date: February 28, 2002
    Inventor: Akio Nakamura
  • Publication number: 20020021946
    Abstract: A throwaway insert for a pin mirror cutter in which eight corners can be used and which the cutting performance and machining accuracy can be increased by making positive the axial rake angle of the peripheral cutting edge. Side faces of a negative insert of a parallelogrammic shape are formed by two surfaces connecting to each other at an angle so as to have a first included angle and a second included angle. Further, independent arcuate surfaces are provided at the intersections between the arcuate corner sides of each of the side faces and the top and bottom surfaces and the intersections between the obtuse corner sides and the top and bottom surfaces.
    Type: Application
    Filed: August 2, 2001
    Publication date: February 21, 2002
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, Ltd.
    Inventors: Shigenori Emoto, Jun Maeda, Akio Nakamura
  • Patent number: 6340842
    Abstract: A semiconductor device provided with one or more semiconductor pellets arranged on the bottom surface of a recess produced along a surface of a semiconductor plate having wirings arranged on the surface thereof, wirings extending toward the surface of the recess, and the recess being filled with a layer of a resin which is inclined to inflate, while it is hardened, resultantly producing a stress in the resin layer to expand toward the side wall of the recess engraved in the semiconductor plate, resultantly preventing breakage from happening for an interface between the side wall of the recess engraved in the semiconductor plate and the surface of the resin layer contacting the side wall, and remarkably improving the thermal conductivity efficiency to reduce the magnitude of a temperature rise of the semiconductor device, resultantly preventing a delay from happening for the operation speed of the semiconductor device.
    Type: Grant
    Filed: December 28, 1998
    Date of Patent: January 22, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Akio Nakamura
  • Patent number: 6333566
    Abstract: A semiconductor device comprises a semiconductor IC chip provided with bond pads on its first surface, a wiring substrate provided with a through hole extending between the opposite surfaces thereof, conductive members electrically connecting the bond pads of the semiconductor IC chip to the conductive lines formed on the wiring substrate respectively, and a sealing resin coating coating the first surface of the semiconductor IC chip and the conductive members, and bonding the side surface of the semiconductor IC chip to the side surface of the through hole of the wiring substrate.
    Type: Grant
    Filed: November 8, 1999
    Date of Patent: December 25, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Akio Nakamura
  • Patent number: 6331203
    Abstract: An aqueous ink for a ball-point pen which is stable over time and has high pigment dispersion stability, includes a pigment, a water-soluble organic solvent, water, xanthane gum of about 0.01 to about 0.2 wt. % and a sodium alginate of about 0.2 to about 0.6 wt. % of a total amount of the ink.
    Type: Grant
    Filed: April 30, 2001
    Date of Patent: December 18, 2001
    Assignee: Kotobuki & Co., Ltd.
    Inventors: Katsuya Hattori, Akio Nakamura, Mikio Morishita
  • Publication number: 20010039110
    Abstract: The sealing resin of a semiconductor device is prevented from being peeled off from the substrate of the semiconductor device. A semiconductor device according to the present invention has a semiconductor substrate containing a central portion having a first thickness and a peripheral portion having a second thickness that is smaller than the first thickness, an electrode pad formed on the semiconductor substrate, a sealing resin for sealing the semiconductor substrate, a protruded electrode formed on the sealing resin, and a wire which electrically connects the electrode pad to the protruded electrode.
    Type: Application
    Filed: July 3, 2001
    Publication date: November 8, 2001
    Inventor: Akio Nakamura
  • Patent number: 6307271
    Abstract: A semiconductor pullet 1 includes an integrated circuit formed in the central area of the pellet 1, first electric pads 2 arranged in a line in the peripheral area and second electric pads 3 connected to the conductive lines 4 each of which has a second width L. The first pad 2 has a first width S1 and arranged with a first interval P. The second pads 3 have a third width S2 and are located outside of the first pads 2 in a parallel line to the line of said first pads with a second interval C. The first, second and third widths S1, L, S2 and the first interval P has the relationship P>S2>S1+L. Each of the second pads 3 are located at the positions corresponding to the middle positions between the first pads 2 adjoining each other where the second pads 3 are located in a first area (region A) which is inside of straight lines from a center of the semiconductor pellet having an angle &thgr; with a side of the semiconductor pellet 1, in which &thgr;>tan−1(2C/(P−S1)).
    Type: Grant
    Filed: March 1, 2000
    Date of Patent: October 23, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Akio Nakamura
  • Publication number: 20010023651
    Abstract: An aqueous ink for a ball-point pen which is stable over time and has high pigment dispersion stability, includes a pigment, a water-soluble organic solvent, water, xanthane gum of about 0.01 to about 0.2 wt. % and a sodium alginate of about 0.2 to about 0.6 wt. % of a total amount of the ink.
    Type: Application
    Filed: April 30, 2001
    Publication date: September 27, 2001
    Inventors: Katsuya Hattori, Akio Nakamura, Mikio Morishita
  • Patent number: 6281591
    Abstract: The sealing resin of a semiconductor device is prevented from being peeled off from the substrate of the semiconductor device. A semiconductor device according to the present invention has a semiconductor substrate containing a central portion having a first thickness and a peripheral portion having a second thickness that is smaller than the first thickness, an electrode pad formed on the semiconductor substrate, a sealing resin for sealing the semiconductor substrate, a protruded electrode formed on the sealing resin, and a wire which electrically connects the electrode pad to the protruded electrode.
    Type: Grant
    Filed: March 6, 2000
    Date of Patent: August 28, 2001
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Akio Nakamura
  • Patent number: 6275816
    Abstract: A aqueous ink for a ball-point pen which is stable over time and has high pigment dispersion stability, includes a pigment, a water-soluble organic solvent, water, xanthane gum of about 0.01 to about 0.2 wt. % and a sodium alginate of about 0.2 to about 0.6 wt. % of a total amount of the ink.
    Type: Grant
    Filed: August 26, 1999
    Date of Patent: August 14, 2001
    Assignee: Kotobuki & Co., LTD
    Inventors: Katsuya Hattori, Akio Nakamura, Mikio Morishita
  • Patent number: 5986333
    Abstract: A semiconductor apparatus includes a semiconductor chip and a die pad on which the semiconductor chip is mounted. The die pad is provided thereon with an opening. The semiconductor chip and the die pad may be shaped to be similar figures of rectangle, and the opening may include a plurality of first slits which are arranged around the corners of the die pad, respectively.
    Type: Grant
    Filed: August 22, 1997
    Date of Patent: November 16, 1999
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Akio Nakamura