Patents by Inventor Akshay Kumar

Akshay Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Digital to analog conversion with correlated electron switch devices
    Patent number: 10148279
    Abstract: Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to digital to analog conversion using correlated electron switch devices ces.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: December 4, 2018
    Assignee: ARM Ltd.
    Inventors: Akshay Kumar, Piyush Agarwal, Bal S. Sandhu, Glen Arnold Rosendale
  • CONTROLLING CURRENT THROUGH CORRELATED ELECTRON SWITCH ELEMENTS DURING PROGRAMMING OPERATIONS
    Publication number: 20180330784
    Abstract: Subject matter disclosed herein may relate to correlated electron switch elements and, more particularly, to controlling current through correlated electron switch elements during programming operations.
    Type: Application
    Filed: May 9, 2017
    Publication date: November 15, 2018
    Inventors: Mudit Bhargava, Glen Arnold Rosendale, Akshay Kumar, Piyush Agarwal, Shidhartha Das
  • BIT-LINE SENSING FOR CORRELATED ELECTRON SWITCH ELEMENTS
    Publication number: 20180330777
    Abstract: To sense an impedance state of one or more correlated electron switch elements, a bit-line may be precharged to a voltage level that is less than a precharge voltage level for a sense amplifier, and a bit-line may be discharged through one or more correlated electron switch elements. A bit-line may be buffered from a sense amplifier via an electronic switch device.
    Type: Application
    Filed: May 9, 2017
    Publication date: November 15, 2018
    Inventors: Piyush Agarwal, Shruti Aggarwal, Mudit Bhargava, Akshay Kumar
  • Power-On-Reset Circuit
    Publication number: 20180331681
    Abstract: Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.
    Type: Application
    Filed: July 23, 2018
    Publication date: November 15, 2018
    Inventors: Lalit Gupta, Vivek Nautiyal, Andy Wangkun Chen, Jitendra Dasani, Bo Zheng, Akshay Kumar, Vivek Asthana
  • Method, system and device for non-volatile memory device operation
    Patent number: 10127981
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: November 13, 2018
    Assignee: ARM Ltd.
    Inventors: Azeez Jennudin Bhavnagarwala, Lucian Shifren, Piyush Agarwal, Akshay Kumar, Robert Campbell Aitken
  • Transferring multiple data sets using a multipath connection
    Patent number: 10129372
    Abstract: Example methods are provided for a first endpoint to transfer a first data set and a second data set to a second endpoint using a multipath connection. The method may comprise detecting the first data set and the second data set from an application executing on the first endpoint for transfer to the second endpoint. The method may comprise, in response to determination that in-order transfer is not required for the first data set and the second data set, establishing a first subflow of a multipath connection with the second endpoint to send the first data set and establishing a second subflow of the multipath connection to send the second data set. The method may further comprise sending the first data set on the first subflow and the second data set on the second subflow to the second endpoint.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: November 13, 2018
    Assignee: NICIRA, INC.
    Inventors: Madhusudhan Ravi, Akshay Kumar Sreeramoju
  • SYSTEMS AND METHODS FOR DATABASE ZONE SHARDING AND API INTEGRATION
    Publication number: 20180314750
    Abstract: Systems and methods are provided to enable control and placement of data repositories. In some embodiments, the system segments data into zones. A website, for example, may need to segment data according to location. In this example, a zone may be created for North America and another zone may be created for Europe. Data related to operations executed in North America, for example, can be placed in the North America zone and data related to transactions in Europe can be placed in the Europe zone. According to some embodiments, the system may use zones to accommodate a range of deployment scenarios.
    Type: Application
    Filed: June 20, 2018
    Publication date: November 1, 2018
    Inventors: Dwight Merriman, Eliot Horowitz, Cory P. Mintz, Cailin Anne Nelson, Akshay Kumar, David Lenox Storch, Charles William Swanson, Keith Bostic, Michael Cahill, Dan Pasette, Mathias Benjamin Stearn, Geert Bosch
  • SYSTEMS AND METHODS FOR DATABASE ZONE SHARDING AND API INTEGRATION
    Publication number: 20180300385
    Abstract: Systems and methods are provided to enable control and placement of data repositories. In some embodiments, the system segments data into zones. A website, for example, may need to segment data according to location. In this example, a zone may be created for North America and another zone may be created for Europe. Data related to operations executed in North America, for example, can be placed in the North America zone and data related to transactions in Europe can be placed in the Europe zone. According to some embodiments, the system may use zones to accommodate a range of deployment scenarios.
    Type: Application
    Filed: June 20, 2018
    Publication date: October 18, 2018
    Inventors: Dwight Merriman, Eliot Horowitz, Cory P. Mintz, Cailin Anne Nelson, Akshay Kumar, David Lenox Storch, Charles William Swanson, Keith Bostic, Michael Cahill, Dan Pasette, Mathias Benjamin Stearn, Geert Bosch
  • Data transfer between endpoints using a multipath connection
    Patent number: 10097465
    Abstract: Example methods are provided to perform data transfer between a first endpoint and a second endpoint. The method may comprise detecting an elephant flow of data from an application executing on the first endpoint for transfer to the second endpoint; and splitting the elephant flow to obtain first packets and second packets. The first endpoint may have cognizance of a first path and a second path between a first network interface of the first endpoint and a second network interface of the second endpoint. The method may comprise establishing a first subflow and a second subflow of a multipath connection with the second endpoint; and sending, over the first network interface, the first packets on the first subflow and the second packets on the second subflow to the second network interface.
    Type: Grant
    Filed: June 8, 2016
    Date of Patent: October 9, 2018
    Assignee: NICIRA INC.
    Inventors: Akshay Kumar Sreeramoju, Madhusudhan Ravi, Benjamin Basler
  • Throughput resilience during link failover
    Patent number: 10097462
    Abstract: Techniques disclosed herein provide an approach for providing throughput resilience during link failover when links are aggregated in a link aggregation group (LAG). In one embodiment, failure of a link in the LAG may be detected, and a Transmission Control Protocol/Interact Protocol (TCP/IP) stack notified to ignore packet losses and not perform network congestion avoidance procedure(s) for one round-trip timeout (RTO) period. In a virtualized system in particular, a virtual switch may be configured to generate events in response to detected link failures and notify TCP/IP stacks of a hypervisor and/or virtual machines (VMs) of the link failures. In turn, the notified TCP/IP stacks of the hypervisor and/or VMs may ignore packet losses and not perform network congestion avoidance procedure(s) for one RTO period.
    Type: Grant
    Filed: August 20, 2016
    Date of Patent: October 9, 2018
    Assignee: Niciria, Inc.
    Inventor: Akshay Kumar Sreeramoju
  • METHOD, SYSTEM AND DEVICE FOR NON-VOLATILE MEMORY DEVICE OPERATION
    Publication number: 20180254084
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.
    Type: Application
    Filed: April 30, 2018
    Publication date: September 6, 2018
    Inventors: Azeez Jennudin Bhavnagarwala, Lucian Shifren, Piyush Agarwal, Akshay Kumar, Robert Campbell Aitken
  • METHOD, SYSTEM AND DEVICE FOR NON-VOLATILE MEMORY DEVICE OPERATION
    Publication number: 20180247693
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain. Additionally, bipolar write operations for set and reset may enable an increased write window and enhanced durability for a CES device.
    Type: Application
    Filed: March 26, 2018
    Publication date: August 30, 2018
    Inventors: Azeez Jennudin Bhavnagarwala, Vivek Asthana, Piyush Agarwal, Akshay Kumar, Lucian Shifren
  • Method, system and device for non-volatile memory device operation
    Patent number: 10062435
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. Limiting current between terminals of the non-volatile memory device during read operations may enable use of higher voltages for higher realized gain.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: August 28, 2018
    Assignee: ARM Ltd.
    Inventors: Azeez Jennudin Bhavnagarwala, Piyush Agarwal, Akshay Kumar
  • Process Variation Detector
    Publication number: 20180233193
    Abstract: Various implementations described herein are directed to an integrated circuit having a memory cell array disposed in a first area of the integrated circuit. The memory cell array may include memory cells with first transistors of multiple types. The integrated circuit may include a process sensor disposed in a second area of the integrated circuit that is different than the first area. The process sensor may include a process detector having second transistors of the multiple types that are separate from the first transistors. The second transistors of the process detector may be arranged for detecting process variation of the memory cells of the memory cell array.
    Type: Application
    Filed: February 16, 2017
    Publication date: August 16, 2018
    Inventors: AKSHAY KUMAR, SAIKAT KUMAR BANIK
  • ELECTRONIC FILTER CIRCUIT
    Publication number: 20180212582
    Abstract: Many kinds of filters are found in electronic circuits and provide a range of signal processing applications. Such filters can be passive, active, analogue or digital and work across a range of frequencies. Present techniques provide an electronic filter circuit comprising resistive and capacitive elements, wherein a resistive element of the filter circuit is provided by a correlated electron material device.
    Type: Application
    Filed: January 20, 2017
    Publication date: July 26, 2018
    Inventors: Bal S. SANDHU, Mudit BHARGAVA, Akshay KUMAR, Piyush AGARWAL, Shidhartha DAS
  • Power-on-reset circuit
    Patent number: 10033376
    Abstract: Various implementations described herein are directed to a circuit. The circuit may include a memory circuit having a first latch. The circuit may include a power-on-reset circuit having a second latch coupled to the first latch. The second latch may be configured to reset the first latch to a predetermined state at power-up.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: July 24, 2018
    Assignee: ARM Limited
    Inventors: Lalit Gupta, Vivek Nautiyal, Andy Wangkun Chen, Jitendra Dasani, Bo Zheng, Akshay Kumar, Vivek Asthana
  • Memory devices formed from correlated electron materials
    Patent number: 10002665
    Abstract: Subject matter provided may relate to devices, such as conducting elements, which operate to place correlated electron switch elements into first and second impedance states. In embodiments, conducting elements are maintained to be at least partially closed continuously during first and second phases of coupling the CES elements between a common source voltage and a corresponding bitline.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: June 19, 2018
    Assignee: ARM Ltd.
    Inventors: Mudit Bhargava, Piyush Agarwal, Akshay Kumar, Glen Arnold Rosendale
  • Method, system and device for non-volatile memory device operation
    Patent number: 9990992
    Abstract: Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a correlated electron switch (CES) device may be placed in any one of multiple memory states in a write operation. A plurality of bitcells may be connectable to a common source voltage during a two-phase operation to place individual bitcells in intended impedance states.
    Type: Grant
    Filed: October 25, 2016
    Date of Patent: June 5, 2018
    Assignee: ARM Ltd.
    Inventors: Azeez Jennudin Bhavnagarwala, Lucian Shifren, Piyush Agarwal, Akshay Kumar, Robert Campbell Aitken
  • DIGITAL TO ANALOG CONVERSION WITH CORRELATED ELECTRON SWITCH DEVICES
    Publication number: 20180152197
    Abstract: Subject matter disclosed herein may relate to correlated electron switch devices, and may relate more particularly to digital to analog conversion using correlated electron switch devices ces.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 31, 2018
    Inventors: Akshay Kumar, Piyush Agarwal, Bal S. Sandhu, Glen Arnold Rosendale
  • Method, system and device for power-up operation
    Patent number: 9972388
    Abstract: Disclosed are methods, systems and devices for powering up devices including non-volatile memory elements in an array of non-volatile memory elements. In one aspect, during a sequence for powering up an integrated device, non-volatile memory elements may be isolated from voltage supplies to avoid in advertent changes of memory states stored in the non-volatile memory elements.
    Type: Grant
    Filed: October 12, 2016
    Date of Patent: May 15, 2018
    Assignee: ARM Ltd.
    Inventors: Shidhartha Das, Piyush Agarwal, Akshay Kumar, Azeez Jennudin Bhavnagarwala