Patents by Inventor Aleksandar Aleksov

Aleksandar Aleksov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11393766
    Abstract: An apparatus is provided which comprises: a plurality of first conductive contacts having a first pitch spacing on a substrate surface, a plurality of second conductive contacts having a second pitch spacing on the substrate surface, and a plurality of conductive interconnects disposed within the substrate to couple a first grouping of the plurality of second conductive contacts associated with a first die site with a first grouping of the plurality of second conductive contacts associated with a second die site and to couple a second grouping of the plurality of second conductive contacts associated with the first die site with a second grouping of the plurality of second conductive contacts associated with the second die site, wherein the conductive interconnects to couple the first groupings are present in a layer of the substrate above the conductive interconnects to couple the second groupings. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Kristof Darmawikarta, Robert A. May, Sri Ranga Sai Boyapati
  • Patent number: 11394094
    Abstract: Generally, this disclosure provides apparatus and systems for coupling waveguides to a server package with a modular connector system, as well as methods for fabricating such a connector system. Such a system may be formed with connecting waveguides that turn a desired amount, which in turn may allow a server package to send a signal through a waveguide bundle in any given direction without bending waveguides.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: July 19, 2022
    Assignee: Intel Corporation
    Inventors: Telesphor Kamgaing, Sasha Oster, Georgios Dogiamis, Adel Elsherbini, Shawna Liff, Aleksandar Aleksov, Johanna Swan, Brandon Rawlings
  • Patent number: 11387187
    Abstract: Embodiments may relate to an interposer that has a first layer with a plurality of first layer pads that may couple with a die. The interposer may further include a second layer with a power delivery component. The interposer may further include a very high density (VHD) layer, that has a VHD pad coupled by a first via with the power delivery component and coupled by a second via with a first layer pad. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Andrew Paul Collins, Jianyong Xie, Sujit Sharan, Henning Braunisch, Aleksandar Aleksov
  • Publication number: 20220216158
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first photodefinable material on at least a portion of the second surface, and a second photodefinable material on at least a portion of the first photodefinable material, wherein the second photodefinable material has a different material composition than the first photodefinable material.
    Type: Application
    Filed: March 23, 2022
    Publication date: July 7, 2022
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Johanna M. Swan
  • Publication number: 20220201843
    Abstract: Embodiments may relate to a microelectronic package or a die thereof which includes a die, logic, or subsystem coupled with a face of the substrate. An inductor may be positioned in the substrate. Electromagnetic interference (EMI) shield elements may be positioned within the substrate and surrounding the inductor. Other embodiments may be described or claimed.
    Type: Application
    Filed: March 15, 2022
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Georgios Dogiamis, Aleksandar Aleksov, Feras Eid, Telesphor Kamgaing, Johanna M. Swan
  • Publication number: 20220196914
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such structures. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, and a second die over the package substrate. In an embodiment, the electronic package further comprises an optical waveguide on the package substrate. In an embodiment, a first end of the optical waveguide is below the first die and a second end of the optical waveguide is below the second die. In an embodiment, the optical waveguide communicatively couples the first die to the second die.
    Type: Application
    Filed: December 22, 2020
    Publication date: June 23, 2022
    Inventors: Jeremy D. ECTON, Hiroki TANAKA, Brandon C. MARIN, Srinivas V. PIETAMBARAM, Gang DUAN, Bai NIE, Haobo CHEN, Zhichao ZHANG, Sai VADLAMANI, Aleksandar ALEKSOV
  • Publication number: 20220199450
    Abstract: Described herein are carrier assemblies, and related devices and methods. In some embodiments, a carrier assembly includes a carrier; a textured material including texturized microstructures coupled to the carrier; and microelectronic components mechanically coupled to the texturized microstructures. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; an electrode on the front side of the carrier; a dielectric material on the electrode; a charging contact on the back side coupled to the electrode; and microelectronic components electrostatically coupled to the front side of the carrier. In some embodiments, a carrier assembly includes a carrier having a front side and a back side; electrodes on the front side; a dielectric material including texturized microstructures on the electrodes; charging contacts on the back side coupled to the plurality of electrodes; and microelectronic components mechanically and electrostatically coupled to the front side of the carrier.
    Type: Application
    Filed: December 23, 2020
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Shawna M. Liff, Johanna M. Swan, Adel A. Elsherbini, Michael J. Baker, Aleksandar Aleksov, Feras Eid
  • Publication number: 20220199546
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, having a first surface and an opposing second surface including a first direct bonding region at the second surface with first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component, having a first surface and an opposing second surface, including a second direct bonding region at the first surface with second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the second microelectronic component is coupled to the first microelectronic component by the first and second direct bonding regions; and a shield structure in the first direct bonding dielectric material at least partially surrounding the one or more of the first metal contacts.
    Type: Application
    Filed: December 18, 2020
    Publication date: June 23, 2022
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Gerald S. Pasdast, Kimin Jun, Zhiguo Qian, Johanna M. Swan, Aleksandar Aleksov, Shawna M. Liff, Mohammad Enamul Kabir, Feras Eid, Kevin P. O'Brien, Han Wui Then
  • Publication number: 20220190806
    Abstract: Embodiments may relate to a die such as an acoustic wave resonator (AWR) die. The die may include a first filter and a second filter in the die body. The die may further include an electromagnetic interference (EMI) structure that surrounds at least one of the filters. Other embodiments may be described or claimed.
    Type: Application
    Filed: March 7, 2022
    Publication date: June 16, 2022
    Applicant: Intel Corporation
    Inventors: Georgios Dogiamis, Aleksandar Aleksov, Feras Eid, Telesphor Kamgaing, Johanna M. Swan
  • Publication number: 20220189861
    Abstract: Disclosed herein are microelectronic assemblies including microelectronic components coupled by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include a first microelectronic component including a first guard ring extending through at least a portion of a thickness of and along a perimeter; a second microelectronic component including a second guard ring extending through at least a portion of a thickness of and along a perimeter, where the first and second microelectronic components are coupled by direct bonding; and a seal ring formed by coupling the first guard ring to the second guard ring. In some embodiments, a microelectronic assembly may include a microelectronic component coupled to an interposer that includes a first liner material at a first surface; a second liner material at an opposing second surface; and a perimeter wall through the interposer and connected to the first and second liner materials.
    Type: Application
    Filed: December 14, 2020
    Publication date: June 16, 2022
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Mohammad Enamul Kabir, Adel A. Elsherbini, Shawna M. Liff, Johanna M. Swan, Feras Eid
  • Publication number: 20220189839
    Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include an interposer; a first microelectronic component having a first surface coupled to the interposer by a first direct bonding region and an opposing second surface; a second microelectronic component having a first surface coupled to the interposer by a second direct bonding region and an opposing second surface; a liner material on the surface of the interposer and around the first and second microelectronic components; an inorganic fill material on the liner material and between the first and second microelectronic components; and a third microelectronic component coupled to the second surfaces of the first and second microelectronic components.
    Type: Application
    Filed: December 15, 2020
    Publication date: June 16, 2022
    Applicant: Intel Corporation
    Inventors: Feras Eid, Johanna M. Swan, Adel A. Elsherbini, Shawna M. Liff, Aleksandar Aleksov
  • Publication number: 20220189850
    Abstract: Disclosed herein are microelectronic assemblies including microelectronic components that are coupled together by direct bonding, and related structures and techniques. In some embodiments, a microelectronic assembly may include an interposer; a first microelectronic component having a first surface coupled to the interposer by a first direct bonding region and an opposing second surface; a second microelectronic component having a first surface coupled to the interposer by a second direct bonding region and an opposing second surface; a liner material on the surface of the interposer and around the first and second microelectronic components; an inorganic fill material on the liner material and between the first and second microelectronic components; and a third microelectronic component coupled to the second surfaces of the first and second microelectronic components.
    Type: Application
    Filed: December 15, 2020
    Publication date: June 16, 2022
    Applicant: Intel Corporation
    Inventors: Shawna M. Liff, Johanna M. Swan, Adel A. Elsherbini, Xavier Francois Brun, Aleksandar Aleksov, Feras Eid
  • Patent number: 11360512
    Abstract: Systems and methods describe herein provide a solution to the technical problem of creating a wearable electronic devices. In particular, these systems and methods enable electrical and mechanical attachment of stretchable or flexible electronics to fabric. A stretchable or flexible electronic platform is bonded to fabric using a double-sided fabric adhesive, and conductive adhesive is used to join pads on the electronic platform to corresponding electrical leads on the fabric. An additional waterproofing material may be used over and beneath the electronic platform to provide a water-resistant or waterproof device This stretchable or flexible electronic platform integration process allows the platform to bend and move with the fabric while protecting the conductive connections. By using flexible and stretchable conductive leads and adhesives, the platform is more flexible and stretchable than traditional rigid electronics enclosures.
    Type: Grant
    Filed: September 11, 2019
    Date of Patent: June 14, 2022
    Assignee: Intel Corporation
    Inventors: Nadine L. Dabby, Sasha N. Oster, Aleksandar Aleksov, Braxton Lathrop, Racquel L Fygenson
  • Publication number: 20220181166
    Abstract: Disclosed herein are integrated circuit (IC) package supports and related apparatuses and methods. For example, in some embodiments, an IC package support may include a non-photoimageable dielectric, and a conductive via through the non-photoimageable dielectric, wherein the conductive via has a diameter that is less than 20 microns. Other embodiments are also disclosed.
    Type: Application
    Filed: February 22, 2022
    Publication date: June 9, 2022
    Applicant: Intel Corporation
    Inventors: Kristof Kuwawi Darmawikarta, Robert May, Sri Ranga Sai Boyapati, Srinivas V. Pietambaram, Chung Kwang Christopher Tan, Aleksandar Aleksov
  • Publication number: 20220181276
    Abstract: Disclosed herein are structures, devices, and methods for electrostatic discharge protection (ESDP) in integrated circuits (ICs). For example, in some embodiments, an IC package support may include: a first conductive structure in a dielectric material; a second conductive structure in the dielectric material; and a material in contact with the first conductive structure and the second conductive structure, wherein the material includes a polymer, and the material is different from the dielectric material. The material may act as a dielectric material below a trigger voltage, and as a conductive material above the trigger voltage.
    Type: Application
    Filed: February 22, 2022
    Publication date: June 9, 2022
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Aleksandar Aleksov, Veronica Aleman Strong
  • Patent number: 11348897
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include: a first die having a first surface and an opposing second surface, first conductive contacts at the first surface of the first die, and second conductive contacts at the second surface of the first die; and a second die having a first surface and an opposing second surface, and first conductive contacts at the first surface of the second die; wherein the second conductive contacts of the first die are coupled to the first conductive contacts of the second die by interconnects, the second surface of the first die is between the first surface of the first die and the first surface of the second die, and a footprint of the first die is smaller than and contained within a footprint of the second die.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Henning Braunisch, Aleksandar Aleksov, Shawna M. Liff, Johanna M. Swan, Patrick Morrow, Kimin Jun, Brennen Mueller, Paul B. Fischer
  • Patent number: 11348882
    Abstract: Embodiments may relate to a microelectronic package with an electrostatic discharge (ESD) protection structure within the package substrate. The ESD protection structure may include a cavity that has a contact of a signal line and a contact of a ground line positioned therein. Other embodiments may be described or claimed.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: May 31, 2022
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Feras Eid, Johanna M. Swan, Adel A. Elsherbini, Veronica Aleman Strong
  • Patent number: 11335641
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate including a dielectric material having a first surface and an opposing second surface, a first photodefinable material on at least a portion of the second surface, and a second photodefinable material on at least a portion of the first photodefinable material, wherein the second photodefinable material has a different material composition than the first photodefinable material.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 17, 2022
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Johanna M. Swan
  • Publication number: 20220149036
    Abstract: Embodiments may relate to a die with a front-end and a backend. The front-end may include a transistor. The backend may include a signal line, a conductive line, and a diode that is communicatively coupled with the signal line and the conductive line. Other embodiments may be described or claimed.
    Type: Application
    Filed: January 21, 2022
    Publication date: May 12, 2022
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel A. Elsherbini, Feras Eid, Veronica Aleman Strong, Johanna M. Swan
  • Patent number: 11329358
    Abstract: Embodiments of the invention include a packaged device with transmission lines that have an extended thickness, and methods of making such device. According to an embodiment, the packaged device may include a first dielectric layer and a first transmission line formed over the first dielectric layer. Embodiments may then include a second dielectric layer formed over the transmission line and the first dielectric layer. According to an embodiment, a first line via may be formed through the second dielectric layer and electrically coupled to the first transmission line. In some embodiments, the first line via extends substantially along the length of the first transmission line.
    Type: Grant
    Filed: April 6, 2020
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Mathew Manusharow, Krishna Bharath, Zhichao Zhang, Yidnekachew S. Mekonnen, Aleksandar Aleksov, Henning Braunisch, Feras Eid, Javier Soto