Patents by Inventor Amitava Chatterjee

Amitava Chatterjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10608110
    Abstract: Metal-oxide-semiconductor (MOS) transistors with reduced subthreshold conduction, and methods of fabricating the same. Transistor gate structures are fabricated in these transistors of a shape and dimension as to overlap onto the active region from the interface between isolation dielectric structures and the transistor active areas. Minimum channel length conduction is therefore not available at the isolation-to-active interface, but rather the channel length along that interface is substantially lengthened, reducing off-state conduction.
    Type: Grant
    Filed: August 17, 2017
    Date of Patent: March 31, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Amitava Chatterjee
  • Publication number: 20180350795
    Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.
    Type: Application
    Filed: August 3, 2018
    Publication date: December 6, 2018
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
  • Publication number: 20180350794
    Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.
    Type: Application
    Filed: August 3, 2018
    Publication date: December 6, 2018
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
  • Patent number: 10128145
    Abstract: Integrated circuits and manufacturing methods are presented for creating diffusion resistors (101, 103) in which the diffusion resistor well is spaced from oppositely doped wells to mitigate diffusion resistor well depletion under high biasing so as to provide reduced voltage coefficient of resistivity and increased breakdown voltage for high-voltage applications.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: November 13, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Kamel Benaissa, Amitava Chatterjee
  • Patent number: 10083951
    Abstract: A semiconductor controlled rectifier (FIG. 4A) for an integrated circuit is disclosed. The semiconductor controlled rectifier comprises a first lightly doped region (100) having a first conductivity type (N) and a first heavily doped region (108) having a second conductivity type (P) formed within the first lightly doped region. A second lightly doped region (104) having the second conductivity type is formed proximate the first lightly doped region. A second heavily doped region (114) having the first conductivity type is formed within the second lightly doped region. A buried layer (101) having the first conductivity type is formed below the second lightly doped region and electrically connected to the first lightly doped region. A third lightly doped region (102) having the second conductivity type is formed between the second lightly doped region and the third heavily doped region.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: September 25, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Akram A. Salman, Farzan Farbiz, Amitava Chatterjee, Xiaoju Wu
  • Patent number: 9865507
    Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: January 9, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Sameer Pendharkar, Amitava Chatterjee
  • Publication number: 20170345929
    Abstract: Metal-oxide-semiconductor (MOS) transistors with reduced subthreshold conduction, and methods of fabricating the same. Transistor gate structures are fabricated in these transistors of a shape and dimension as to overlap onto the active region from the interface between isolation dielectric structures and the transistor active areas. Minimum channel length conduction is therefore not available at the isolation-to-active interface, but rather the channel length along that interface is substantially lengthened, reducing off-state conduction.
    Type: Application
    Filed: August 17, 2017
    Publication date: November 30, 2017
    Inventor: Amitava Chatterjee
  • Patent number: 9768296
    Abstract: Metal-oxide-semiconductor (MOS) transistors with reduced subthreshold conduction, and methods of fabricating the same. Transistor gate structures are fabricated in these transistors of a shape and dimension as to overlap onto the active region from the interface between isolation dielectric structures and the transistor active areas. Minimum channel length conduction is therefore not available at the isolation-to-active interface, but rather the channel length along that interface is substantially lengthened, reducing off-state conduction.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: September 19, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Amitava Chatterjee
  • Patent number: 9721849
    Abstract: A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: August 1, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Derek W. Robinson, Amitava Chatterjee
  • Patent number: 9583596
    Abstract: An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: February 28, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philipp Steinmann, Amitava Chatterjee, Sameer Pendharkar
  • Patent number: 9577094
    Abstract: An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.
    Type: Grant
    Filed: October 16, 2015
    Date of Patent: February 21, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Shaoping Tang, Amitava Chatterjee, Imran Mahmood Khan, Kaiping Liu
  • Publication number: 20160372376
    Abstract: A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types.
    Type: Application
    Filed: September 2, 2016
    Publication date: December 22, 2016
    Inventors: Derek W. ROBINSON, Amitava CHATTERJEE
  • Publication number: 20160322263
    Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
    Type: Application
    Filed: July 7, 2016
    Publication date: November 3, 2016
    Inventors: Pinghai Hao, Sameer Pendharkar, Amitava Chatterjee
  • Patent number: 9461035
    Abstract: A CMOS integrated circuit containing an isolated n-channel DEMOS transistor and an isolated vertical PNP transistor has deep n-type wells and surrounding shallow n-type wells providing isolation from the p-type substrate. The isolated n-channel DEMOS transistor has an upper n-type layer providing an extended drain, and a lower p-type layer isolating the extended drain from the underlying deep n-type well. The isolated vertical PNP transistor has an upper n-type layer providing a base and a lower p-type layer providing a collector. A CMOS integrated circuit having opposite polarities of the transistors may be formed by appropriate reversals in dopant types.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: October 4, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Derek W. Robinson, Amitava Chatterjee
  • Patent number: 9431302
    Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: August 30, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Sameer Pendharkar, Amitava Chatterjee
  • Patent number: 9412668
    Abstract: Impurity atoms of a first type are implanted through a gate and a thin gate dielectric into a channel region that has substantially only the first type of impurity atoms at a middle point of the channel region to increase the average dopant concentration of the first type of impurity atoms in the channel region to adjust the threshold voltage of a transistor.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: August 9, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Pinghai Hao, Sameer Pendharkar, Amitava Chatterjee
  • Patent number: 9397164
    Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: July 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Brian E. Hornung, Xiang-Zheng Bo, Amitava Chatterjee, Alwin J. Tsao
  • Publication number: 20160079392
    Abstract: An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.
    Type: Application
    Filed: November 23, 2015
    Publication date: March 17, 2016
    Inventors: Philipp Steinmann, Amitava Chatterjee, Sameer Pendharkar
  • Publication number: 20160079364
    Abstract: An integrated circuit and method having a deep collector vertical bipolar transistor with a first base tuning diffusion. A MOS transistor has a second base tuning diffusion. The first base tuning diffusion and the second base tuning diffusion are formed using the same implant.
    Type: Application
    Filed: November 18, 2015
    Publication date: March 17, 2016
    Inventors: Brian E. Hornung, Xiang-Zheng Bo, Amitava Chatterjee, Alwin J. Tsao
  • Publication number: 20160035890
    Abstract: An integrated circuit and method includes a DEMOS transistor with improved CHC reliability that has a lower resistance surface channel under the DEMOS gate that transitions to a lower resistance subsurface channel under the drain edge of the DEMOS transistor gate.
    Type: Application
    Filed: October 16, 2015
    Publication date: February 4, 2016
    Inventors: Shaoping TANG, Amitava CHATTERJEE, Imran Mahmood KHAN, Kaiping LIU