Patents by Inventor Amitava Chatterjee

Amitava Chatterjee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100164004
    Abstract: A method of fabricating an integrated circuit (IC) including a plurality of MOS transistors and ICs therefrom include providing a substrate having a silicon including surface, and forming a plurality of dielectric filled trench isolation regions in the substrate, wherein the silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. A first silicon including layer is deposited, wherein the first silicon including extends from a surface of the trench isolation regions over the trench isolation active area edges to the silicon including surface. The first silicon including layer is completely oxidized to convert the first silicon layer to a silicon oxide layer, wherein the silicon oxide layer provides at least a portion of a gate dielectric for at least one of the plurality of MOS transistors.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 1, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: AMITAVA CHATTERJEE, SEETHARAMAN SRIDHAR, XIAOJU WU, VLADIMIR F. DROBNY
  • Publication number: 20100163997
    Abstract: A method of fabricating an integrated circuit (IC) and ICs therefrom including a plurality of Metal Oxide Semiconductor (MOS) transistors having reduced gate dielectric thinning and corner sharpening at the trench isolation/semiconductor edge for gate dielectric layers generally 500 to 5,000 Angstroms thick. The method includes providing a substrate having a silicon including surface. A plurality of dielectric filled trench isolation regions are formed in the substrate. The silicon including surface forms trench isolation active area edges along its periphery with the trench isolation regions. An epitaxial silicon comprising layer is deposited, wherein the epitaxial comprising silicon layer is formed over the silicon comprising surface.
    Type: Application
    Filed: December 29, 2008
    Publication date: July 1, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Vladimir F. DROBNY, Amitava CHATTERJEE, Phillipp STEINMANN, Rick WISE
  • Patent number: 7662688
    Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: February 16, 2010
  • Patent number: 7638402
    Abstract: A sidewall spacer pullback scheme is implemented in forming a transistor. The scheme, among other things, allows silicide regions of the transistor to be made larger, or rather have a larger surface area. The larger surface area has a lower resistance and thus allows voltages to be applied to the transistor more accurately. The scheme also allows transistors to be made slightly thinner so that the formation of voids in a layer of dielectric material formed over the transistors is mitigated. This mitigates yield loss by facilitating more predictable or otherwise desirable transistor behavior.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: December 29, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Mahalingam Nandakumar, Amitava Chatterjee, Terrence J. Riley
  • Publication number: 20090258471
    Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
    Type: Application
    Filed: June 22, 2009
    Publication date: October 15, 2009
  • Publication number: 20090134471
    Abstract: One embodiment relates to an integrated circuit that includes at least one semiconductor device. The integrated circuit includes a first contact associated with a first terminal of the semiconductor device. The first contact spans a dielectric layer and couples the first terminal to an interconnect line that communicates signals horizontally on the integrated circuit, where the interconnect line has a first composition. The integrated circuit further includes a second contact associated with a second terminal of the semiconductor device. The second contact spans the dielectric layer and couples the second terminal to a landing pad to which a via is coupled, where the landing pad has a second composition that differs from the first composition. Other circuits and methods are also disclosed.
    Type: Application
    Filed: November 26, 2007
    Publication date: May 28, 2009
    Inventors: Amitava Chatterjee, Howard Tigelaar, Victor Sutcliffe
  • Patent number: 7514331
    Abstract: A method of manufacturing a semiconductor device comprising removing a first oxide layer deposited over a semiconductor substrate, thereby exposing source and drain regions of the substrate. The first oxide layer is configured as an etch-stop for forming silicon nitride sidewall spacers of a gate structure located adjacent to the source and drain regions. The method further comprises depositing a second oxide layer selectively on the exposed source and drain regions and then removing lateral segments of the silicon nitride sidewall spacers.
    Type: Grant
    Filed: June 8, 2006
    Date of Patent: April 7, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Jong Shik Yoon, Amitava Chatterjee, Haowen Bu
  • Publication number: 20080160708
    Abstract: A sidewall spacer pullback scheme is implemented in forming a transistor. The scheme, among other things, allows silicide regions of the transistor to be made larger, or rather have a larger surface area. The larger surface area has a lower resistance and thus allows voltages to be applied to the transistor more accurately. The scheme also allows transistors to be made slightly thinner so that the formation of voids in a layer of dielectric material formed over the transistors is mitigated. This mitigates yield loss by facilitating more predictable or otherwise desirable transistor behavior.
    Type: Application
    Filed: March 27, 2007
    Publication date: July 3, 2008
    Inventors: Mahalingam Nandakumar, Amitava Chatterjee, Terrence J. Riley
  • Publication number: 20080096292
    Abstract: A method for measuring interface traps in a MOSFET, comprising measuring charge pumping current of a pulse wave form for various frequencies over a predetermined frequency range, creating plotted points of the measured charge pumping current versus the predetermined frequency range, determining the total number of interface traps participating in the charge pumping current by calculating the slope of a best fit line through the plotted points.
    Type: Application
    Filed: October 20, 2006
    Publication date: April 24, 2008
    Inventors: Tathagata Chatterjee, Amitava Chatterjee
  • Publication number: 20080003772
    Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
    Type: Application
    Filed: August 30, 2007
    Publication date: January 3, 2008
  • Patent number: 7314800
    Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
    Type: Grant
    Filed: December 7, 2005
    Date of Patent: January 1, 2008
  • Publication number: 20070287258
    Abstract: A method of manufacturing a semiconductor device comprising removing a first oxide layer deposited over a semiconductor substrate, thereby exposing source and drain regions of the substrate. The first oxide layer is configured as an etch-stop for forming silicon nitride sidewall spacers of a gate structure located adjacent to the source and drain regions. The method further comprises depositing a second oxide layer selectively on the exposed source and drain regions and then removing lateral segments of the silicon nitride sidewall spacers.
    Type: Application
    Filed: June 8, 2006
    Publication date: December 13, 2007
    Applicant: Texas Instruments Incorporated
    Inventors: Jong Shik Yoon, Amitava Chatterjee, Haowen Bu
  • Publication number: 20070287239
    Abstract: Methods are disclosed for forming an SRAM cell having symmetrically implanted active regions and reduced cross-diffusion therein. One method comprises patterning a resist layer overlying a semiconductor substrate to form resist structures about symmetrically located on opposite sides of active regions of the cell, implanting one or more dopant species using a first implant using the resist structures as an implant mask, rotating the semiconductor substrate relative to the first implant by about 180 degrees, and implanting one or more dopant species into the semiconductor substrate with a second implant using the resist structures as an implant mask. A method of performing a symmetric angle implant is also disclosed to provide reduced cross-diffusion within the cell, comprising patterning equally spaced resist structures on opposite sides of the active regions of the cell to equally shadow laterally opposed first and second angled implants.
    Type: Application
    Filed: June 12, 2006
    Publication date: December 13, 2007
  • Patent number: 7285830
    Abstract: An improved lateral bipolar junction transistor and a method of forming such a lateral bipolar transistor without added mask in CMOS flow on a p-substrate are disclosed. The CMOS flow includes patterning and n-well implants; pattern and implant pocket implants for core nMOS and MOS; pattern and implants pocket implants I/O nMOS and pMOS; sidewall deposit and etch and then source/drain pattern and implant for nMOS and pMOS. The bipolar transistor is formed by forming emitter and collector contacts by implants used in source/drain regions; forming an emitter by implants done in core pMOS during core pMOS LDD extender; and forming part of an base by pocket implant steps.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: October 23, 2007
    Assignee: Texas Instruments Incorporated
    Inventor: Amitava Chatterjee
  • Patent number: 7279397
    Abstract: A method (200) of forming an isolation structure is presented, in which a hard mask layer (304, 308) is formed (204, 206) over the isolation and active regions (305, 303) of a semiconductor body (306), and a dopant is selectively provided to a portion of the active region (303) proximate the isolation region (305) to create a threshold voltage compensation region (318). After the compensation region (318) is created, the hard mask layer (304, 308) is patterned (218) to create a patterned hard mask. The patterned hard mask is then used in forming (222) a trench (323) in the isolation region (305) near the compensation region (318), and the trench (323) is then filled (224) with a dielectric material (338).
    Type: Grant
    Filed: July 27, 2004
    Date of Patent: October 9, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Manoj Mehrotra, Amitava Chatterjee
  • Patent number: 7229869
    Abstract: The present invention provides a method for manufacturing a semiconductor device and a method for manufacturing an integrated circuit. The method for manufacturing the semiconductor device, among other steps, includes forming a gate structure (130) over a substrate (110), the gate structure (130) having L-shaped sidewall spacers (430) on opposing sidewalls thereof and placing source/drain implants (310 or 510) into the substrate (110) proximate the gate structure (130). The method for manufacturing the semiconductor device further includes removing at least a portion of a horizontal segment of the L-shaped sidewall spacers (430).
    Type: Grant
    Filed: March 8, 2005
    Date of Patent: June 12, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Jong Shik Yoon, Shirin Siddiqui, Amitava Chatterjee, Brian E. Goodlin, Karen H. R. Kirmse
  • Patent number: 7216310
    Abstract: The present invention provides a method (100) of designing a circuit. The method comprises specifying (105) a design parameter for memory transistors and logic transistors and selecting (110) a test retention-mode bias voltage for the memory transistors. The method further comprises determining (115) a first relationship of a retention-mode leakage current and the design parameter at the test retention-mode bias voltage and obtaining (120) a second relationship of an active-mode drive current and the design parameter. The first and second relationships are used (125) to assess whether there is a range of values of the design parameter where the retention-mode leakage current and the active-mode drive current are within a predefined circuit specification. The method also includes adjusting (130) the test retention-mode bias voltage and repeating the determining and the using if the retention-mode total leakage current or the active-mode drive current is outside of the predefined circuit specification.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: May 8, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Amitava Chatterjee, David Barry Scott, Theodore W. Houston, Song Zhao, Shaoping Tang, Zhiqiang Wu
  • Patent number: 7193277
    Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: March 20, 2007
  • Patent number: 7141468
    Abstract: The present invention facilitates semiconductor device fabrication by providing mechanisms for utilizing different isolation schemes within embedded memory and other logic portions of a device. The isolation mechanism of the embedded memory portion is improved relative to other portions of the device by increasing dopant concentrations or reducing the depth of the dopant profiles within well regions of the embedded memory array. As a result, smaller isolation spacing can be employed thereby permitting a more compact array. The isolation mechanism of the logic portion is relatively less than that of the embedded memory portion, which permits greater operational speed for the logic.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: November 28, 2006
  • Publication number: 20060228867
    Abstract: A method (10) of forming an isolation structure (140, 142) in a semiconductor substrate (102) is disclosed, wherein the isolation structure (140, 142) can be formed in a controlled manner so as to regulate stresses exerted by the structure on one or more active regions (106) of the substrate (102) located adjacent to the structure (140, 142).
    Type: Application
    Filed: April 12, 2005
    Publication date: October 12, 2006
    Inventors: Manoj Mehrotra, Amitava Chatterjee, Jin Zhao