Patents by Inventor Amitava Majumdar
Amitava Majumdar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240153062Abstract: A method of predicting virtual metrology data for a wafer lot that includes receiving first image data from an imager system, the first image data relating to at least one first wafer lot, receiving measured metrology data from metrology equipment relating to the at least one first wafer lot, applying one or more machine learning techniques to the first image data and the measured metrology data to generate at least one predictive model for predicting at least one of virtual metrology data or virtual cell metrics data of wafer lots, and utilizing the at least one generated predictive model to generate at least one of first virtual metrology data or first virtual cell metrics data for the first wafer lot.Type: ApplicationFiled: January 8, 2024Publication date: May 9, 2024Inventors: Amitava Majumdar, Qianlan Liu, Pradeep Ramachandran, Shawn D. Lyonsmith, Steve K. McCandless, Ted L. Taylor, Ahmed N. Noemaun, Gordon A. Haller
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Patent number: 11961556Abstract: Methods, systems, and devices supporting a socket design for a memory device are described. A die may include one or more memory arrays, which each may include any number of word lines and any number of bit lines. The word lines and the bit lines may be oriented in different directions, and memory cells may be located at the intersections of word lines and bit lines. Sockets may couple the word lines and bit lines to associated drivers, and the sockets may be located such that memory cells farther from a corresponding word line socket are nearer a corresponding bit line socket, and vice versa. For example, sockets may be disposed in rows or regions that are parallel to one another, and which may be non-orthogonal to the corresponding word lines and bit lines.Type: GrantFiled: January 4, 2022Date of Patent: April 16, 2024Assignee: Micron Technology, Inc.Inventors: Amitava Majumdar, Radhakrishna Kotti, Rajasekhar Venigalla
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Publication number: 20240096439Abstract: In a compute express link (CXL) memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, steps are taken to determine if the memory location requires no repair, soft repair, or hard repair. The data is corrected and written back to a new memory location which is memory-mapped to the original location, thus effecting the soft- or hard-repair. The present system and method does not repair the entire row of memory, but only repairs the specific die(s) that exhibit memory error in the row.Type: ApplicationFiled: February 15, 2023Publication date: March 21, 2024Applicant: Micron Technology, Inc.Inventors: Amitava Majumdar, Greg S. Hendrix, Anandhavel Nagendrakumar, Krunal Patel, Kirthi Shenoy, Danilo Caraccio, Ankush Lal, Frank F. Ross, Adam D. Gailey
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Publication number: 20240096438Abstract: In a memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, the data is corrected and written back to the same memory location. The memory location is re-read. If bit errors are again identified, the memory location is marked for soft or hard repair. If, upon rereading the memory location, additional bit errors are identified, a historical record of memory errors is reviewed to determine if bit errors have occurred previously at the same memory location. If yes, the memory location is again marked for a soft post package repair or a hard post package repair.Type: ApplicationFiled: February 15, 2023Publication date: March 21, 2024Applicant: Micron Technology, Inc.Inventors: Amitava Majumdar, Greg S. Hendrix, Anandhavel Nagendrakumar, Krunal Patel, Kirthi Shenoy, Danilo Caraccio, Ankush Lal, Frank F. Ross, Adam D. Gailey
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Publication number: 20240095120Abstract: In a memory controller system, a system and method to identify memory errors which may require soft package repair or hard package repair to rows of DRAM memory. When data is written to a row of DRAM, the data is immediately and automatically read back and scanned for bit errors. If bit errors are identified, the data is corrected and written back to the same memory location. The memory location is re-read. If bit errors are again identified, the memory location is marked for soft or hard repair. If, upon rereading the memory location, additional bit errors are identified, a historical record of memory errors is reviewed to determine if bit errors have occurred previously at the same memory location. If yes, the memory location is again marked for a soft post package repair or a hard post package repair.Type: ApplicationFiled: February 15, 2023Publication date: March 21, 2024Applicant: Micron Technology, Inc.Inventors: Amitava Majumdar, Greg S. Hendrix, Anandhavel Nagendrakumar, Krunal Patel, Kirthi Shenoy, Danilo Caraccio, Ankush Lal, Frank F. Ross, Adam D. Gailey
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Publication number: 20240036762Abstract: Systems, apparatuses, and methods related to bloom filter implementation into a controller are described. A memory device is coupled to a memory controller. The memory controller is configured to implement a counting bloom filter, increment the counting bloom filter in response to a row activate command of the memory device, determine whether a value of the counting bloom filter exceeds a threshold value, and perform an action in response to the value exceeding the threshold value.Type: ApplicationFiled: July 27, 2023Publication date: February 1, 2024Inventors: Edmund J. Gieske, Cagdas Dirik, Elliott C. Cooper-Balis, Robert M. Walker, Amitava Majumdar, Sujeet Ayyapureddi, Yang Lu, Ameen D. Akel, Niccolò Izzo, Danilo Caraccio, Markus H. Geiger
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Patent number: 11869178Abstract: A method of predicting virtual metrology data for a wafer lot that includes receiving first image data from an imager system, the first image data relating to at least one first wafer lot, receiving measured metrology data from metrology equipment relating to the at least one first wafer lot, applying one or more machine learning techniques to the first image data and the measured metrology data to generate at least one predictive model for predicting at least one of virtual metrology data or virtual cell metrics data of wafer lots, and utilizing the at least one generated predictive model to generate at least one of first virtual metrology data or first virtual cell metrics data for the first wafer lot.Type: GrantFiled: December 10, 2020Date of Patent: January 9, 2024Assignee: Micron Technology, Inc.Inventors: Amitava Majumdar, Qianlan Liu, Pradeep Ramachandran, Shawn D. Lyonsmith, Steve K. McCandless, Ted L. Taylor, Ahmed N. Noemaun, Gordon A. Haller
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Patent number: 11860228Abstract: An integrated circuit (IC) chip device includes testing interface circuity and testing circuitry to test the operation of the IC chips of the IC chip device. The IC chip device includes a first IC chip that comprises first testing circuitry. The first testing circuitry receives a mode select signal, a clock signal, and encoded signals, and comprises finite state machine (FSM) circuitry, decoder circuitry, and control circuitry. The FSM circuitry determines an instruction based on the mode select signal and the clock signal. The decoder circuitry decodes the encoded signals to generate a decoded signal. The control circuitry generates a control signal from the instruction and the decoded signal. The control signal indicates a test to be performed by the first testing circuitry.Type: GrantFiled: May 11, 2022Date of Patent: January 2, 2024Assignee: XILINX, INC.Inventors: Albert Shih-Huai Lin, Niravkumar Patel, Amitava Majumdar, Jane Wang Sowards
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Publication number: 20230393770Abstract: Systems, methods, and apparatus for memory device security and row hammer mitigation are described. A control mechanism may be implemented in a front-end and/or a back-end of a memory sub-system to refresh rows of the memory. A row activation command having a row address at control circuitry of a memory sub-system and incrementing a first count of a row counter corresponding to the row address stored in a content addressable memory (CAM) of the memory sub-system may be received. Control circuitry may determine whether the first count is greater than a row hammer threshold (RHT) minus a second count of a CAM decrease counter (CDC); the second count may be incremented each time the CAM is full. A refresh command to the row address may be issued when a determination is made that the first count is greater than the RHT minus the second count.Type: ApplicationFiled: September 16, 2022Publication date: December 7, 2023Inventors: Yang Lu, Sujeet Ayyapureddi, Edmund J. Gieske, Cagdas Dirik, Ameen D. Akel, Elliott C. Cooper-Balis, Amitava Majumdar, Robert M. Walker, Danilo Caraccio
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Publication number: 20230366929Abstract: An integrated circuit (IC) chip device includes testing interface circuitry and testing circuitry to test the operation of the IC chips of the IC chip device. The IC chip device includes a first IC chip that comprises first testing circuitry. The first testing circuitry receives a mode select signal, a clock signal, and encoded signals, and comprises finite state machine (FSM) circuitry, decoder circuitry, and control circuitry. The FSM circuitry determines an instruction based on the mode select signal and the clock signal. The decoder circuitry decodes the encoded signals to generate a decoded signal. The control circuitry generates a control signal from the instruction and the decoded signal. The control signal indicates a test to be performed by the first testing circuitry.Type: ApplicationFiled: May 11, 2022Publication date: November 16, 2023Inventors: Albert Shih-Huai LIN, Niravkumar PATEL, Amitava MAJUMDAR, Jane Wang SOWARDS
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Patent number: 11782830Abstract: This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.Type: GrantFiled: December 20, 2021Date of Patent: October 10, 2023Assignee: Micron Technologies, Inc.Inventors: Amitava Majumdar, Sandeep Krishna Thirumala, Lingming Yang, Karthik Sarpatwari, Nevil N. Gajera
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Patent number: 11775431Abstract: This document describes apparatuses and techniques for cache memory with randomized eviction. In various aspects, a cache memory randomly selects a cache line for eviction and/or replacement. The cache memory may also support multi-occupancy whereby the cache memory enters data reused from another cache line to replace the data of the randomly evicted cache line. By so doing, the cache memory may operate in a nondeterministic fashion, which may increase a probability of data remaining in the cache memory for subsequent requests.Type: GrantFiled: December 20, 2021Date of Patent: October 3, 2023Assignee: Micron Technologies, Inc.Inventors: Amitava Majumdar, Sandeep Krishna Thirumala, Lingming Yang, Karthik Sarpatwari, Nevil N. Gajera
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Publication number: 20230297285Abstract: An apparatus can include a number of memory devices and a memory controller coupled to one or more of the number of memory devices. The memory controller can include a row hammer detector. The memory controller can be configured increment for a first time period a row counter in a first data structure and a refresh counter. The memory controller can be configured to increment for a second time period a row counter in a second data structure and the refresh counter. The memory controller can be configured to determine that a value of the refresh counter exceeds a refresh threshold and responsive to the determination that the value of the refresh counter exceeds the refresh threshold, issue a notification.Type: ApplicationFiled: March 15, 2023Publication date: September 21, 2023Inventors: Amitava Majumdar, Anandhavel Nagendrakumar, Mohammed Ebrahim Hargan, Scott Garner, Danilo Caraccio, Daniele Balluchi, Chia Wei Chang, Ankush Lal
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Publication number: 20230298951Abstract: Test structures for wafers are disclosed. A device may include a silicon wafer including a number of die and a scribe area between two die of the number of die. The scribe area may include one or more test structures. The test structures may include a p-doped region and an n-doped region adjacent to the p-doped region. The test structures may also include a first contact electrically coupled to the p-doped region and a second contact electrically coupled to the n-doped region. The second contact may be proximate to the first contact. Associated devices, systems, and methods are also disclosed.Type: ApplicationFiled: March 16, 2022Publication date: September 21, 2023Inventors: Chase M. Hunter, Marlon W. Hug, Stephen W. Russell, Rajesh Kamana, Amitava Majumdar, Radhakrishna Kotti, Ahmed N. Noemaun, Tejaswi K. Indukuri
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Publication number: 20230290189Abstract: Embodiments herein describe wrapping non-safety compliant hardware resources with error detection checking to satisfy a safety standard. Doing so permits non-safety compliant hardware to be used to perform one or more tasks in a system that, as a whole, satisfies a particular safety standard (e.g., one of the ASIL QM, A, B, C, and D grades).Type: ApplicationFiled: March 10, 2022Publication date: September 14, 2023Inventors: Yanran CHEN, Sagheer AHMAD, Amitava MAJUMDAR, Pramod BHARDWAJ
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Patent number: 11755804Abstract: An integrated circuit includes an intellectual property core, scan data pipeline circuitry configured to convey scan data to the intellectual property core, and scan control pipeline circuitry configured to convey one or more scan control signals to the intellectual property core. The integrated circuit also includes a wave shaping circuit configured to detect a trigger event on the one or more scan control signals and, in response to detecting the trigger event, suppress a scan clock to the intellectual property core for a selected number of clock cycles.Type: GrantFiled: December 28, 2021Date of Patent: September 12, 2023Assignee: Xilinx, Inc.Inventors: Albert Shih-Huai Lin, Rambabu Nerukonda, Niravkumar Patel, Amitava Majumdar
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Publication number: 20230282258Abstract: Systems and methods for finite time counting period counting of infinite data streams is presented. In particular example systems and methods enable counting row accesses to a memory media device over predetermined time intervals in order to deterministically detect row hammer attacks on the memory media device. Example embodiments use two identical tables that are reset at times offset in relation to each other in a ping-pong manner in order to ensure that there exists no false negative detections. The counting techniques described in this disclosure can be used in various types of row hammer mitigation techniques and can be implemented in content addressable memory or another type of memory. The mitigation may be implemented on a per-bank basis, per-channel basis or per-memory media device basis. The memory media device may be a dynamic random access memory type device.Type: ApplicationFiled: January 26, 2023Publication date: September 7, 2023Applicant: Micron Technology, Inc.Inventors: Edmund GIESKE, Amitava MAJUMDAR, Cagdas DIRIK, Sujeet AYYAPUREDDI, Yang LU, Ameen D. AKEL, Danilo CARACCIO, Niccolo' IZZO, Elliott C. COOPER-BALIS, Markus H. GEIGER
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Publication number: 20230267996Abstract: Systems, methods and apparatus to program a memory cell to have a threshold voltage to a level representative of one value among more than two predetermined values. A first voltage pulse is driven across the memory cell to cause a predetermined current to go through the memory cell. The first voltage pulse is sufficient to program the memory cell to a level representative of a first value. To program the memory cell to a level representative of a second value, a second voltage pulse, different from the first voltage pulse, is driven across the memory cell within a time period of residual poling in the memory cell caused by the first voltage pulse.Type: ApplicationFiled: May 2, 2023Publication date: August 24, 2023Inventors: Lingming Yang, Xuan Anh Tran, Karthik Sarpatwari, Francesco Douglas Verna-Ketel, Jessica Chen, Nevil N. Gajera, Amitava Majumdar
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Publication number: 20230260565Abstract: Practical, energy-efficient, and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The mitigation may be implemented on a per-bank basis. The memory media device may be DRAM.Type: ApplicationFiled: August 30, 2022Publication date: August 17, 2023Applicant: Micron Technology, Inc.Inventors: Edmund GIESKE, Sujeet AYYAPUREDDI, Yang LU, Amitava MAJUMDAR
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Publication number: 20230236735Abstract: Systems and methods for area-efficient mitigation of errors that are caused by row hammer attacks and the like in a memory media device are described. The counters for counting row accesses are maintained in a content addressable memory (CAM) the provides fast access times. The detection of errors is deterministically performed while maintaining a number of row access counters that is smaller than the total number of rows protected in the memory media device. The circuitry for the detection and mitigation may be in the memory media device or in a memory controller to which the memory media device attaches. The memory media device may be dynamic random access memory (DRAM).Type: ApplicationFiled: August 29, 2022Publication date: July 27, 2023Applicant: Micron Technology, Inc.Inventors: Sujeet AYYAPUREDDI, Yang LU, Edmund GIESKE, Cagdas DIRIK, Ameen D. AKEL, Elliott C. COOPER-BALIS, Amitava MAJUMDAR, Danilo CARACCIO, Robert M. WALKER