Abstract: Disclosed are novel methods and apparatus for efficiently providing instruction-based BIST of external memory. In an embodiment, a built-in self-testing system is disclosed. The system includes an external memory module, an on-chip memory controller coupled to the external memory module, an on-chip built-in self-test (BIST) module coupled to the on-chip memory controller, and an interface controller coupled to the BIST module to provide an interface to access the BIST module. The on-chip memory controller may send and receive data to and from the external memory module. And, the BIST module may include an instruction register to store a plurality of instructions.

Abstract: Methods and systems for automated memory test modeling generation and validation are provided. Information supplied by a graphical user interface is used to generate a customized memory primitive. The memory primitive subsequently undergoes a two phase validation to test for correct functioning.

Abstract: A method generates and verifies a design-for-test (DFT) library for an automatic test pattern generator (ATPG) tool. The method includes (a) creating a synthesis library including primitives to be used to create the modules, the primitives being the same as primitives used by the ATPG tool, (b) creating a register transfer level (RTL) description for each module, (c) performing synthesis using the synthesis library and the RTL description to create a gate level description for each module, and (d) generating the DFT library by converting a hardware description language (HDL) of the gate level description into a script language for the ATPG tool to create a DFT file for each module. The method may further include (e) converting the DFT files into a RTL description to create a pseudo-RTL description for each module, and (f) comparing the RTL description and the pseudo-RTL description for verification of the DFT library.

Abstract: Disclosed are novel methods and apparatus for efficiently providing instruction-based BIST of memory interconnects. In an embodiment of the present invention, a method of testing a memory interconnect between an external memory module and a chip is disclosed. The method includes: providing an on-chip memory controller coupled to the external memory module, the on-chip memory controller sending and receiving data to and from the external memory module; providing an on-chip built-in self-test (BIST) module coupled to the on-chip memory controller, the BIST module including an instruction register to store a plurality of instructions; testing the external memory module; and once the external memory module has successfully passed the testing, utilizing the external memory module in testing the memory interconnect.

Abstract: Disclosed are novel methods and apparatus for efficiently providing instruction-based BIST of external memory. In an embodiment, a built-in self-testing system is disclosed. The system includes an external memory module, an on-chip memory controller coupled to the external memory module, an on-chip built-in self-test (BIST) module coupled to the on-chip memory controller, and an interface controller coupled to the BIST module to provide an interface to access the BIST module. The on-chip memory controller may send and receive data to and from the external memory module. And, the BIST module may include an instruction register to store a plurality of instructions.

Abstract: A method of transforming a stand-alone verification test for a functional block into a serial scan test pattern for detecting manufacturing defects includes designing a functional block based on a set of design considerations; generating a parallel functional pattern for testing the functional block; and translating the parallel functional pattern into a serial pattern. An apparatus for transforming a stand-alone verification test for a functional block into a serial scan test pattern for detecting manufacturing defects, comprising a functional block designed based on a set of design considerations and comprising a scan boundary, the scan boundary comprising a scan in chain and a scan out chain, a parallel functional pattern for testing the functional block; and software for translating the parallel functional pattern into a serial pattern that is fed into the scan in chain, evaluated, and fed out of the scan out chain.

Abstract: Methods and systems for automated memory test modeling generation and validation are provided. Information supplied by a graphical user interface is used to generate a customized memory primitive. The memory primitive subsequently undergoes a two phase validation to test for correct functioning.

Abstract: A method for analyzing a scan dump assigns a first latch to a first value, compares the first latch output to the first value for spatial alignment. The method then assigns a second latch to either a second or third value. The second value corresponds to before an event. The third value corresponds to after an event and may be incremented with ongoing clock cycles.

Abstract: A circuit for efficiently performing shadow logic testing and memory block testing within a semiconductor integrated circuit. The integrated circuit includes a memory block for storing data. A shadow logic circuit is coupled to the memory block for interfacing the memory block with external circuitry. The shadow logic provides inputs to the memory block and receives data outputs from the memory block. A test collar is coupled between the memory block and the shadow logic. The test collar receives the data inputs from the shadow logic and receives the data outputs from the memory block. The test collar is configured to both provide test inputs to the shadow logic and capture test outputs from the shadow logic independent of the memory block. The test collar is also adapted to both provide tests inputs to the memory block and capture test outputs from the memory block independent of the shadow logic.

Abstract: A circuit for efficiently performing shadow logic testing and memory block testing within a semiconductor integrated circuit. The integrated circuit includes a memory block for storing data. A shadow logic circuit is coupled to the memory block for interfacing the memory block with external circuitry. The shadow logic provides inputs to the memory block and receives data outputs from the memory block. A test collar is coupled between the memory block and the shadow logic. The test collar receives the data inputs from the shadow logic and receives the data outputs from the memory block. The test collar is configured to both provide test inputs to the shadow logic and capture test outputs from the shadow logic independent of the memory block. The test collar is also adapted to both provide tests inputs to the memory block and capture test outputs from the memory block independent of the shadow logic.

Abstract: The method of controlling ground bounce during DC parametric tests disclosed herein is based on the formulation of tests that best achieve two broad goals. The first goal is to reduce the number of I/O pins that are switched simultaneously. In the formulation of the VIL and VIH tests this goal is implemented by preferably only switching one input at a time. The second goal is to simultaneously switch I/O pins that are distant from one another. In the formulation of the VOL and VOH tests this goal is implemented by partitioning the outputs into subsets and selecting preferably one and only one output at a time from each and every subset.