Abstract: An apparatus may comprise a controller to retrieve data from a non-volatile memory, and an error correction module operable on the controller to read a memory cell of the non-volatile memory at a first set of sense conditions comprising a multiplicity of sense conditions. The error correction module may be further operable to set a first set of bits in an encoded output, the first set of bits comprising a logical state bit to indicate a logical state of the memory cell and one or more additional bits in the encoded output to indicate accuracy of the logical state bit based upon results of the read at the first set of sense conditions, the first set of sense conditions comprising a greater number than that of the first set of bits. Other embodiments are disclosed and claimed.

Abstract: In its many embodiments, the present invention provides a method of inhibiting one or more cyclin dependent kinases in a patient comprising administering to said patient a therapeutically effective amount of at least one pyrazolo[1,5-a]pyrimidine compound or a pharmaceutical composition comprising such compound, and methods of treatment, prevention, inhibition, or amelioration of one or more diseases associated with the CDKs using such compounds or pharmaceutical compositions.

Abstract: An implantable medical electrical lead includes a plurality of conductors that extend continuously, without any intermediary junctions, between a plurality of electrodes and a corresponding plurality of contact members of an in-line connector terminal. A junction between each conductor and the corresponding contact member is preferably formed by first fitting a conductive sleeve, which is coupled to a proximal portion of the conductor, into an eyelet feature of the contact member, which is mounted on a strut member, and then welding the sleeve to the contact member at a pre-formed slot of the contact member, which extends along an external recessed surface thereof. The assembly of the connector terminal preferably completes the construction of the lead, wherein the proximal portion of each conductor is positioned in a helical path, which extends between an elongate body of the lead and the connector terminal, and along which a grip zone is formed.

Abstract: An exemplary system for crimping a prosthetic valve comprises a radially expandable and compressible prosthetic valve, a crimping device positioned around the valve and configured to reduce the diameter of the valve to a delivery configuration, and a sterile package enclosing the valve and the crimping device. The valve can be pre-assembled in a partially crimped configuration within the crimping device. After removing the sterile packaging, the crimping device can be used to crimp the valve from the partially crimped configuration to the delivery configuration, such as by twisting a knob on the crimping device. The system can further comprise at least a portion of a delivery catheter within the sterile package, wherein the valve is pre-mounted on or adjacent to an inflatable balloon of the delivery catheter, such that the valve can be crimped onto the delivery catheter using the crimping device.

Abstract: The present invention involves synthesizing conducting polymer nanofibers by mixing an oxidant solution with a monomer solution, which includes a monomer and an oligomer of the monomer that is used as an initiator. The oxidant solution includes an oxidizing agent, or oxidant, such as ferric chloride to oxidize the monomer, the oligomer, or both, and begin polymerization. By including an initiator in the form of the oligomer, which may have a lower oxidation potential than the monomer, the rate of polymerization is accelerated, resulting in the nanofibrous morphology. Therefore, the conducting polymer nanofibers may be synthesized without the use of surfactants, hard templates, or seeds, resulting in a simplified and accelerated polymerization process, which enhances homogenous nucleation of the conducting polymer nanofibers.

Abstract: An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.

Abstract: A structure and method for fabricating silicide contacts for semiconductor devices is provided. Specifically, the structure and method involves utilizing chemical vapor deposition (CVD) and annealing to form silicide contacts of different shapes, selectively on regions of a semiconductor field effect transistor (FET), such as on source and drain regions. The shape of silicide contacts is a critical factor that can be manipulated to reduce contact resistance. Thus, the structure and method provide silicide contacts of different shapes with low contact resistance, wherein the silicide contacts also mitigate leakage current to enhance the utility and performance of FETs in low power applications.

Abstract: A system and method for detecting changes by comparing images which cover the same physical area but are collected at different times, the system comprising: at least one input for inputting an image of a target area; the image of the target area having signatures representing outstanding features; at least one processor operating to divide the image of a target area into a plurality of target subimages; at least one memory comprising reference data comprising reference subimages taken at or near the target area at various times, the at least one processor operating to determine a sparse image representation from the reference data; the sparse image representation of the target data being a linear combination of reference data from corresponding reference subimages stored in the at least one memory; the at least one processor operating to compare the target image to the sparse image representation and to match signatures from the target image to the sparse image representation to register the images and perfo

Abstract: A contact via hole is formed through at least one dielectric layer over a semiconductor substrate. A semiconductor material is deposited at the bottom of the contact via hole and atop the at least one dielectric layer by ion cluster deposition. An angled oxygen cluster deposition is performed to convert portions of the semiconductor material on the top surface of the at least one dielectric layer into a semiconductor oxide, while oxygen is not implanted into the deposited semiconductor material at the bottom of the contact via hole. A metal semiconductor alloy is formed at the bottom of the contact hole by deposition of a metal and an anneal. The semiconductor oxide at the top of the at least one dielectric layer can be removed during a preclean before metal deposition, a postclean after metal semiconductor alloy formation, and/or during planarization for forming contact via structures.

Abstract: A multi-stage silicidation process is described wherein a dielectric etch to expose contact regions is timed to be optimal for a highest of the contact regions. After exposing the highest of the contact regions, a silicide is formed on the exposed contact region and the dielectric is re-etched, selective to the formed silicide, to expose another contact region, lower than the highest of the contact regions, without recessing the highest of the contact regions. The process then forms a silicide on the lower contact region. The process may continue to varying depths. Each subsequent etch is performed without the use of additional masking steps. By manipulating diffusive properties of existing silicides and deposited metals, the silicides formed on contact regions with differing depths/height may comprise different compositions and be optimized for different polarity devices such as nFET and pFET devices.

Abstract: An implantable medical electrical lead includes a plurality of conductors that extend continuously, without any intermediary junctions, between a plurality of electrodes and a corresponding plurality of contact members of an in-line connector terminal. A junction between each conductor and the corresponding contact member is preferably formed by first fitting a conductive sleeve, which is coupled to a proximal portion of the conductor, into an eyelet feature of the contact member, which is mounted on a strut member, and then welding the sleeve to the contact member at a pre-formed slot of the contact member, which extends along an external recessed surface thereof. The assembly of the connector terminal preferably completes the construction of the lead, wherein the proximal portion of each conductor is positioned in a helical path, which extends between an elongate body of the lead and the connector terminal, and along which a grip zone is formed.

Abstract: This is a device for occluding a space, for example an aneurysm, within the body. In particular, the device comprising a metallic vaso-occlusive device and expandable fibrous elements. The devices may be placed in a desired site within a mammal.

Abstract: This invention relates to the design and implementation of a large family of fast, efficient, hardware-friendly fixed-point multiplierless inverse discrete cosine transforms (IDCT) and the corresponding forward transform counterparts. All of the proposed structures comprises of butterflies and dyadic-rational lifting steps that can be implemented using only shift-and-add operations. The approach also allows the computational scalability with different accuracy-versus-complexity trade-offs. Furthermore, the lifting construction allows a simple construction of the corresponding multiplierless forward DCT, providing bit-exact reconstruction if properly pairing with our proposed IDCT. With appropriately-chosen parameters, all of the disclosed structures can easily pass IEEE-1180 test.

Abstract: Techniques for segmenting an object at a self-checkout are provided. The techniques include capturing an image of an object at a self-checkout, dividing the image into one or more blocks, computing a confidence value for each of the one or more blocks, and eliminating one or more blocks from consideration based on the confidence value for each of the one or more blocks, wherein the one or more blocks remaining map to a region of the image containing the object.

Abstract: Methods form an integrated circuit structure by forming at least a portion of a plurality of devices within and/or on a substrate and patterning trenches in an inter-layer dielectric layer on the substrate adjacent the devices. The patterning forms relatively narrow trenches and relatively wide trenches. The methods then perform an angled implant of a compensating material into the trenches. The angle of the angled implant implants a greater concentration of the compensating material in the regions of the substrate at the bottom of the wider trenches relative to an amount of compensating material implanted in the regions of the substrate at the bottom of the narrower trenches. The methods then deposit a metallic material within the trenches and heat the metallic material to form silicide from the metallic material.

Abstract: Techniques are provided. The techniques include capturing an image of an object at a self-checkout, dividing the image into one or more blocks, computing one or more features of the image, computing a confidence value for each of the one or more blocks, wherein computing a confidence value for each of the one or more blocks comprises using a minimum feature distance from one or more reference background blocks, and eliminating one or more blocks from consideration via use of an adaptive threshold computed on the confidence value for each of the one or more blocks, wherein the one or more blocks remaining map to a region of the image containing the object.

Abstract: A multi-stage silicidation process is described wherein a dielectric etch to expose contact regions is timed to be optimal for a highest of the contact regions. After exposing the highest of the contact regions, a silicide is formed on the exposed contact region and the dielectric is re-etched, selective to the formed silicide, to expose another contact region, lower than the highest of the contact regions, without recessing the highest of the contact regions. The process then forms a silicide on the lower contact region. The process may continue to varying depths. Each subsequent etch is performed without the use of additional masking steps. By manipulating diffusive properties of existing silicides and deposited metals, the silicides formed on contact regions with differing depths/height may comprise different compositions and be optimized for different polarity devices such as nFET and pFET devices.

Abstract: An embodiment of a circuit is described that includes a first inductor comprising a first end and a second end, where the first end of the first inductor forms an input node of the circuit. The embodiment of the circuit further includes a second inductor comprising a first end and a second end, where the second end of the first inductor is coupled to the first end of the second inductor forming an output node of the circuit; a resistor coupled to the second end of the second inductor; and an electrostatic discharge structure coupled to the output node and configured to provide an amount of electrostatic discharge protection, where the amount of electrostatic discharge protection is based on a parasitic bridge capacitance and a load capacitance metric.

Abstract: An integrated circuit device includes an input/output (IO) pad, and a programmable termination capacitance circuit coupled to the IO pad, the programmable termination capacitance circuit comprising at least one compensation bank, wherein each of the at least one compensation bank includes a compensation capacitor coupled to a reference voltage through a compensation pass gate.

Abstract: A technique for collecting and correlating locking data collects and correlates information on a plurality of programs waiting on or holding a plurality of resources in a multi-computer database system. The technique identifies a program executing on one computer of the multi-computer database system that is waiting on a resource. The technique also identifies a second program, executing on another computer, as the ultimate holder of the resource. An operator display screen displays information corresponding to the first program and the second program. The operator display screen may be switched between a multiline display format and a single line display format. The collection, identification, and display of the locking data is performed periodically, to allow the operator to discover locking problems and take a desired corrective action.