Patents by Inventor An D. Tran

An D. Tran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20130069124
    Abstract: An MOSFET device having a Silicide layer of uniform thickness, and methods for its fabrication, are provided. One such method involves depositing a metal layer over wide and narrow contact trenches on the surface of a silicon semiconductor substrate. Upon formation of a uniformly thin amorphous intermixed alloy layer at the metal/silicon interface, the excess (unreacted) metal is removed. The device is annealed to facilitate the formation of a thin silicide layer on the substrate surface which exhibits uniform thickness at the bottoms of both wide and narrow contact trenches.
    Type: Application
    Filed: September 20, 2011
    Publication date: March 21, 2013
    Applicants: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES INC.
    Inventors: Bin Yang, Christian Lavoie, Emre Alptekin, Ahmet S. Ozcan, Cung D. Tran, Mark Raymond
  • Patent number: 8395446
    Abstract: Method and apparatus for amplification in an IC are described. A dual mode isolation amplifier having two modes of operation is provided. In the first mode of operation for a resistor-loaded differential transconductance with additional gain, a first switch circuit is placed in a substantially nonconductive state for electrically decoupling from a first current source node and a second current source node. A second switch circuit is placed in a substantially conductive state for electrically coupling a capacitor thereof to the first current source node and the second current source node. At high frequencies, a first resistance associated with the capacitor coupled in parallel with a resistive load is substantially reduced. The resistive load is coupled between the first current source node and the second current source node. The first resistance is reduced by approximating a short circuit by the capacitor during high-frequency operation.
    Type: Grant
    Filed: January 22, 2010
    Date of Patent: March 12, 2013
    Assignee: Xilinx, Inc.
    Inventor: Toan D. Tran
  • Publication number: 20130030519
    Abstract: Described herein are systems and methods from delivering prosthetic devices, such as prosthetic heart valves, through the body and into the heart for implantation therein. The prosthetic devices delivered with the delivery systems disclosed herein are, for example, radially expandable from a radially compressed state mounted on the delivery system to a radially expanded state for implantation using an inflatable balloon of the delivery system. Exemplary delivery routes through the body and into the heart include transfemoral routes, transapical routes, and transaortic routes, among others.
    Type: Application
    Filed: July 26, 2012
    Publication date: January 31, 2013
    Applicant: EDWARDS LIFESCIENCES CORPORATION
    Inventors: Tri D. Tran, Ronaldo Cayabyab, David J. Evans, Sean Chow, Christopher Chia
  • Publication number: 20130020705
    Abstract: Methods form an integrated circuit structure by forming at least a portion of a plurality of devices within and/or on a substrate and patterning trenches in an inter-layer dielectric layer on the substrate adjacent the devices. The patterning forms relatively narrow trenches and relatively wide trenches. The methods then perform an angled implant of a compensating material into the trenches. The angle of the angled implant implants a greater concentration of the compensating material in the regions of the substrate at the bottom of the wider trenches relative to an amount of compensating material implanted in the regions of the substrate at the bottom of the narrower trenches. The methods then deposit a metallic material within the trenches and heat the metallic material to form silicide from the metallic material.
    Type: Application
    Filed: July 20, 2011
    Publication date: January 24, 2013
    Applicants: GLOBALFOUNDRIES, INC., INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Emre Alptekin, Viraj Y. Sardesai, Cung D. Tran, Bin Yang
  • Publication number: 20120239124
    Abstract: An implantable medical electrical lead includes a plurality of conductors that extend continuously, without any intermediary junctions, between a plurality of electrodes and a corresponding plurality of contact members of an in-line connector terminal. A junction between each conductor and the corresponding contact member is preferably formed by first fitting a conductive sleeve, which is coupled to a proximal portion of the conductor, into an eyelet feature of the contact member, which is mounted on a strut member, and then welding the sleeve to the contact member at a pre-formed slot of the contact member, which extends along an external recessed surface thereof. The assembly of the connector terminal preferably completes the construction of the lead, wherein the proximal portion of each conductor is positioned in a helical path, which extends between an elongate body of the lead and the connector terminal, and along which a grip zone is formed.
    Type: Application
    Filed: March 18, 2011
    Publication date: September 20, 2012
    Applicant: Medtronic, Inc.
    Inventors: Yaling Fan, Douglas N. Hess, Megan M. Kruse, Nathan Lee Olson, Kathryn R. Parsons, Vu D. Tran, Gareth Morgan
  • Publication number: 20120209375
    Abstract: A delivery system for stabilizing a catheter shaft across an aortic arch can include one or more stabilizing members configured to fix or stabilize the position of the catheter relative to the aortic arch of a patient.
    Type: Application
    Filed: February 9, 2012
    Publication date: August 16, 2012
    Inventors: Gilbert Madrid, Matthew T. Winston, Sam Sok, Thanh Huy Le, Tri D. Tran, Kim Le
  • Patent number: 8236637
    Abstract: A planar silicide structure and method of fabrication is disclosed. A FET having a silicided raised source-drain structure is formed where the height of the source-drain structures are the same as the height of the gates, simplifying the process of forming contacts on the FET. One embodiment utilizes a replacement metal gate FET and another embodiment utilizes a gate-first FET.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: August 7, 2012
    Assignee: International Business Machines Corporation
    Inventors: Henry K. Utomo, Sameer Hemchand Jain, Ravikumar Ramachandran, Cung D. Tran
  • Publication number: 20120188671
    Abstract: An embodiment of a circuit is described that includes a first inductor comprising a first end and a second end, where the first end of the first inductor forms an input node of the circuit. The embodiment of the circuit further includes a second inductor comprising a first end and a second end, where the second end of the first inductor is coupled to the first end of the second inductor forming an output node of the circuit; a resistor coupled to the second end of the second inductor; and an electrostatic discharge structure coupled to the output node and configured to provide an amount of electrostatic discharge protection, where the amount of electrostatic discharge protection is based on a parasitic bridge capacitance and a load capacitance metric.
    Type: Application
    Filed: April 6, 2012
    Publication date: July 26, 2012
    Applicant: Xilinx, Inc.
    Inventors: Vassili Kireev, James Karp, Toan D. Tran
  • Patent number: 8217682
    Abstract: Embodiments of an integrated circuit driver, a method for operating integrated circuit driver, and predrivers are described. In one embodiment of the integrated circuit driver, a bias control circuit provides a bias signal for a first mode and a second mode. The bias signal has a first voltage level associated with operation in the first mode and a second voltage level associated with operation in the second mode. An output driver circuit receives the bias signal. In the first mode, the output driver circuit operates as a supply referenced driver, and in the second mode, the output driver circuit operates as a ground referenced driver.
    Type: Grant
    Filed: August 10, 2010
    Date of Patent: July 10, 2012
    Assignee: Xilinx, Inc.
    Inventors: Greg W. Starr, Toan D. Tran
  • Patent number: 8181140
    Abstract: A method of generating a circuit design comprising a T-coil network includes determining inductance for inductors and a parasitic bridge capacitance of the T-coil network. The parasitic bridge capacitance is compared with a load capacitance metric that depends upon parasitic capacitance of a load coupled to an output of the T-coil network. An amount of electrostatic discharge (ESD) protection of the circuit design that is coupled to the output of the T-coil network and/or a parameter of the inductors of the T-coil network is selectively adjusted according to the comparison. The circuit design, which can specify inductance of the inductors, the amount of ESD protection, and/or the width of windings of the inductors, is outputted.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: May 15, 2012
    Assignee: Xilinx, Inc.
    Inventors: Vassili Kireev, James Karp, Toan D. Tran
  • Publication number: 20120091402
    Abstract: The present invention involves synthesizing conducting polymer nanofibers by mixing an oxidant solution with a monomer solution, which includes a monomer and an oligomer of the monomer that is used as an initiator. The oxidant solution includes an oxidizing agent, or oxidant, such as ferric chloride to oxidize the monomer, the oligomer, or both, and begin polymerization. By including an initiator in the form of the oligomer, which may have a lower oxidation potential than the monomer, the rate of polymerization is accelerated, resulting in the nanofibrous morphology. Therefore, the conducting polymer nanofibers may be synthesized without the use of surfactants, hard templates, or seeds, resulting in a simplified and accelerated polymerization process, which enhances homogenous nucleation of the conducting polymer nanofibers.
    Type: Application
    Filed: December 22, 2011
    Publication date: April 19, 2012
    Applicant: The Regents of the University of California
    Inventors: Richard B. Kaner, Koo Shin, Henry Hiep D. Tran
  • Patent number: 8155462
    Abstract: A reconstruction system for digital signals processed by the laplacian pyramid including a master lifting-based parameterization reconstruction scheme. The system also involves the design of low-complexity FIR linear-phase integer-coefficient filtering operators for lapacian pyramid decimation and interpolation stages that deliver a minimum mean-squared error reconstruction.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: April 10, 2012
    Assignee: FastVDO, LLC
    Inventors: Trac D. Tran, Lijie Liu, Pankaj N. Topiwala
  • Publication number: 20120074503
    Abstract: A planar silicide structure and method of fabrication is disclosed. A FET having a silicided raised source-drain structure is formed where the height of the source-drain structures are the same as the height of the gates, simplifying the process of forming contacts on the FET.
    Type: Application
    Filed: September 29, 2010
    Publication date: March 29, 2012
    Applicant: International Business Machines Corporation
    Inventors: Henry K. Utomo, Sameer Hemchand Jain, Ravikumar Ramachandran, Cung D. Tran
  • Publication number: 20120063689
    Abstract: A method of identifying an object in an image includes selecting a portion of a target image of a target object, selecting a corresponding window portion of a reference image of a reference object from at least one reference image of at least one reference object, the position of the window portion within the reference image corresponding to the position of the portion of the target image within the target image, generating a reference set including a plurality of different portions of the reference image from within the window portion, determining a weighted combination of the plurality of different portions from the reference set approximating the portion of the target image, and determining whether the target object matches the reference object based on the weighted combination.
    Type: Application
    Filed: September 15, 2011
    Publication date: March 15, 2012
    Applicant: The Johns Hopkins University
    Inventors: Trac D. Tran, Chen Yi, Thong T. Do
  • Patent number: 8129436
    Abstract: The present invention provides a method for simplifying manufacture of a mixed alcohol or mixed oxygenate product from synthesis gas. The mixed alcohol or mixed oxygenate product contains ethanol and other oxygenates with two or more carbon atoms per molecule. The method includes stripping a portion of carbon dioxide and inert gases contained in a mixed alcohol synthesis reaction product using a methanol-containing stream, such as one produced as part of the method, as a medium to absorb said carbon dioxide and inert gases and recycling light products and heavy products to one or more of synthesis gas generation, mixed alcohol synthesis and separation of desired mixed alcohol or mixed oxygenate products from other components of a mixed alcohol synthesis stream.
    Type: Grant
    Filed: March 21, 2007
    Date of Patent: March 6, 2012
    Assignee: Dow Global Technologies LLC
    Inventors: Max M. Tirtowidjojo, Barry B. Fish, Hendrik L. Pelt, Dennis W. Jewell, Mark D. Bearden, John G. Pendergast, Jr., Jon H. Siddall, Brien A. Stears, Haivan D. Tran, Jan W. Verwijs, Aaltje Verwijs-van den Brink, legal representative, Lena Verwijs, legal representative, Hendrika Gerrita Verwijs, legal representative, Richard M. Wehmeyer
  • Publication number: 20120027297
    Abstract: Techniques for segmenting an object at a self-checkout are provided. The techniques include capturing an image of an object at a self-checkout, dividing the image into one or more blocks, computing one or more features of the image, computing a confidence value for each of the one or more blocks, wherein computing a confidence value for each of the one or more blocks comprises using a minimum feature distance from one or more reference backgound blocks, and eliminating one or more blocks from consideration via use of an adaptive threshold computed on the confidence value for each of the one or more blocks, wherein the one or more blocks remaining map to a region of the image containing the object.
    Type: Application
    Filed: July 27, 2010
    Publication date: February 2, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rogerio S. Feris, Charles A. Otto, Sharathchandra Pankanti, Duan D. Tran
  • Patent number: D672902
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: December 18, 2012
    Assignee: ABL IP Holding LLC
    Inventors: Patrick A. Collins, Long D. Tran, Daniel Edward Sicking, Thomas Edward Harris, John T. Hickok, Michael R. Miller
  • Patent number: D672909
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: December 18, 2012
    Assignee: ABL IP Holding LLC
    Inventors: Patrick A. Collins, Long D. Tran, Daniel Edward Sicking, Thomas Edward Harris, John T. Hickok, Michael R. Miller
  • Patent number: D677825
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: March 12, 2013
    Assignee: ABL IP Holding LLC
    Inventors: Patrick A. Collins, Long D. Tran, Daniel Edward Sicking, Thomas Edward Harris, John T. Hickok, Michael R. Miller
  • Patent number: D678592
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: March 19, 2013
    Assignee: ABL IP Holding LLC
    Inventors: Patrick A. Collins, Long D. Tran, Daniel Edward Sicking, Thomas Edward Harris, John T. Hickok, Michael R. Miller