Patents by Inventor An-Tung Chen

An-Tung Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11604552
    Abstract: A metal mesh structure includes at least one first wire extending along a first direction and at least one second wire extending along a second direction different from the first direction. The at least one first wire includes a first portion, a second portion and a first bending portion connected between the first portion and the second portion. The first bending portion crosses the at least one second wire to form a node. An extending line of the first portion along the first direction passes through the node and is overlapped with the second portion. A first included angle is included between the first direction and the second direction, and a second included angle is included between the first bending portion and the at least one second wire, wherein the first included angle is different from the second included angle, and the second included angle is 90 degrees.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: March 14, 2023
    Assignee: HENGHAO TECHNOLOGY CO., LTD.
    Inventors: Yu-Tung Chen, Shan-Chen Huang, Yu-Yuan Yeh
  • Patent number: 11600653
    Abstract: Methods for forming via last through-vias. A method includes providing an active device wafer having a front side including conductive interconnect material disposed in dielectric layers and having an opposing back side; providing a carrier wafer having through vias filled with an oxide extending from a first surface of the carrier wafer to a second surface of the carrier wafer; bonding the front side of the active device wafer to the second surface of the carrier wafer; etching the oxide in the through vias in the carrier wafer to form through oxide vias; and depositing conductor material into the through oxide vias to form conductors that extend to the active carrier wafer and make electrical contact to the conductive interconnect material. An apparatus includes a carrier wafer with through oxide vias extending through the carrier wafer to an active device wafer bonded to the carrier wafer.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: March 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Szu-Ying Chen, Pao-Tung Chen, Dun-Nian Yaung, Jen-Cheng Liu
  • Publication number: 20230034954
    Abstract: A domain security assurance system includes a computing platform having processing hardware and a memory storing software code. The processing hardware is configured to execute the software code to obtain domain inventory data identifying multiple domains, to predict, using the domain inventory data, which of the domains are owned by the same entity to identify commonly owned domains, and to determine, using the domain inventory data and the commonly owned domains, which of the commonly owned domains are controlled by the same administrator to identify one or more group(s) of commonly administered domains. When executed, the software code also removes, using the domain inventory data, duplicate domains included in the group(s) to identify non-duplicate domains, evaluates a susceptibility of each of the non-duplicate domains to a cyber-attack to identify one or more target domain(s) vulnerable to the cyber-attack, and identifies the target domain(s) for a security assessment.
    Type: Application
    Filed: July 27, 2021
    Publication date: February 2, 2023
    Inventors: Wen Tung Chen, Preetjot Singh, Christine Tang
  • Patent number: 11552027
    Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: January 10, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chien, Chien-Hsien Tseng, Dun-Nian Yaung, Nai-Wen Cheng, Pao-Tung Chen, Yi-Shin Chu, Yu-Yang Shen
  • Patent number: 11545443
    Abstract: A method for forming a hybrid-bonding structure is provided. The method includes forming a first dielectric layer over a first semiconductor substrate. The first semiconductor substrate includes a conductive structure. The method also includes partially removing the first dielectric layer to form a first dielectric dummy pattern, a second dielectric dummy pattern and a third dielectric dummy pattern and an opening through the first dielectric layer. The first dielectric dummy pattern, the second dielectric dummy pattern and the third dielectric dummy pattern are surrounded by the opening. In addition, the method includes forming a first conductive line in the opening. The first conductive line is in contact with the conductive structure.
    Type: Grant
    Filed: September 24, 2020
    Date of Patent: January 3, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Ming Wu, Kuan-Liang Liu, Pao-Tung Chen
  • Patent number: 11532661
    Abstract: A semiconductor device includes a first semiconductor chip including a first substrate, a plurality of first dielectric layers and a plurality of conductive lines formed in the first dielectric layers over the first substrate. The semiconductor device further includes a second semiconductor chip having a surface bonded to a first surface of the first semiconductor chip, the second semiconductor chip including a second substrate, a plurality of second dielectric layers and a plurality of second conductive lines formed in the second dielectric layers over the second substrate. The semiconductor device further includes a first conductive feature extending from the first semiconductor chip to one of the plurality of second conductive lines, and a first seal ring structure extending from the first semiconductor chip to the second semiconductor chip.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Ying Ho, Pao-Tung Chen, Wen-De Wang, Jen-Cheng Liu, Dun-Nian Yaung
  • Publication number: 20220396585
    Abstract: The present invention relates to compounds of formula I: in which p, q, Y1, Y2, R1, R2a, R2b, R3a, R3b, R4a, R4b, R5a, R5b, R7 and R8 are defined in the Summary of the Invention; capable of inhibiting the activity of SHP2. The invention further provides a process for the preparation of compounds of the invention, pharmaceutical preparations comprising such compounds and methods of using such compounds and compositions in the management of diseases or disorders associated with the aberrant activity of SHP2.
    Type: Application
    Filed: February 23, 2021
    Publication date: December 15, 2022
    Inventors: Christine Hiu-Tung Chen, Zhuoliang Chen, Michael Dore, Jorge Garcia Fortanet, John William Giraldes, Rajesh Karki, Mitsunori Kato, Matthew J. LaMarche, Lawrence Blas Perez, Martin Sendzik, Troy Douglas Smith, Bakary-Barry Toure, Sarah Williams
  • Publication number: 20220387684
    Abstract: A portable hemodialysis system is provided including a dialyzer, a closed loop blood flow path which transports blood from a patient through the dialyzer and back to the patient, and a closed loop dialysate flow path which transports dialysate through the dialyzer. Preferably, the hemodialysis system includes a sorbent filter in the dialysate flow path. Furthermore, the hemodialysis machine includes a blood pump, and a pair of dialysate pumps. A processor controls the flow of blood through the blood flow path, and the processor controls the flow of dialysate through the dialysate flow path. In addition, the processor stores a patient treatment plan wherein the flow rate of the dialysate through the dialysate flow path reduces throughout the patient's treatment to maximize the amount of urea removed by the sorbent filter.
    Type: Application
    Filed: May 28, 2021
    Publication date: December 8, 2022
    Applicant: DIALITY INC.
    Inventors: Brandon Borillo, Tzu Tung Chen, Clayton Poppe
  • Publication number: 20220378995
    Abstract: A portable hemodialysis system is provided comprising a dialyzer, having a dialysate-replenishing system for replenishing minerals of dialysate in the dialyzer, the dialysate-replenishing system includes: a sorbent filter configured to remove ammonia from the dialysate, the sorbent filter having an outlet that outputs the dialysate to a dialysate flow path; a first reagent source containing a first reagent solution; a first pump configured to inject the first reagent solution into the dialysate flow path; a first mixer coupled to the dialysate flow path and downstream of the first pump, the first mixer configured to mix the dialysate with the first reagent solution; a conductivity sensor configured to measure a level of dissolved solids in the dialysate after the first mixer; and a controller configured to adjust a flow rate of the first reagent solution by adjusting the first pump based at least on the level of measured levels.
    Type: Application
    Filed: May 27, 2022
    Publication date: December 1, 2022
    Inventors: Brandon Borillo, Tzu Tung Chen, Clayton Poppe
  • Publication number: 20220378992
    Abstract: A portable hemodialysis system is provided including a dialyzer, a closed loop blood flow path which transports blood from a patient through the dialyzer and back to the patient, and a closed loop dialysate flow path which transports dialysate through the dialyzer. Preferably, the hemodialysis system comprises a sorbent filter in the dialysate flow path. Furthermore, the hemodialysis system comprises a dialysate quality sensor disposed directly in the dialysate flow path. The dialysate quality sensor is configured to change color based on a pH level, ammonia level, or ammonium level of the dialysate.
    Type: Application
    Filed: May 27, 2022
    Publication date: December 1, 2022
    Inventors: Brandon Borillo, Tzu Tung Chen, Clayton Poppe
  • Publication number: 20220378994
    Abstract: Sorbent regeneration systems for use in dialysis machines are described. Sorbent regeneration cartridges may include a layer of urease, a layer of acid zirconium phosphate, and a layer of sodium zirconium phosphate. An apparatus for conducting dialysis may include a sorbent cartridge, and a dialyzer in fluid communication with the sorbent cartridge, wherein spent dialysate passes from the dialyzer to and through the sorbent cartridge, and wherein the sorbent cartridge comprises a layer of urease, a layer of acid zirconium phosphate, and a layer of sodium zirconium phosphate. The urease may be immobilized to or associated with a carrier.
    Type: Application
    Filed: May 26, 2022
    Publication date: December 1, 2022
    Inventors: Brandon Borillo, Tzu Tung Chen
  • Patent number: 11514617
    Abstract: A method for providing a virtual environment during movement is provided. The method includes the following operations: capturing a first image associated with an interior space of a housing and also associated with part of an external environment captured outward from the interior space; classifying the first image into a first segment associated with the interior space and a second segment associated with the part of the external environment; estimating a first pose and a second pose of a mobile device associated with respective the housing and the external environment, in which the first pose is estimated by a first localization model based on the first segment, and the second pose is estimated by a second localization model based on a second image associated with the external environment; and displaying virtual objects by the mobile device according to the first and second poses.
    Type: Grant
    Filed: August 13, 2021
    Date of Patent: November 29, 2022
    Assignee: HTC Corporation
    Inventors: Shih-Chieh Kuo, Yuan-Tung Chen, Wan-Ling Yang
  • Publication number: 20220350235
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Application
    Filed: June 30, 2022
    Publication date: November 3, 2022
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Publication number: 20220348553
    Abstract: The present invention relates to compounds of formula I: in which m, Y1, Y2, Y3, R1, R2a, R2b, R3a, R3b, R4a, R4b, R5a and R5b are defined in the Summary of the Invention; capable of inhibiting the activity of SHP2. The invention further provides a process for the preparation of compounds of the invention, pharmaceutical preparations comprising such compounds and methods of using such compounds and compositions in the management of diseases or disorders associated with the aberrant activity of SHP2.
    Type: Application
    Filed: June 24, 2022
    Publication date: November 3, 2022
    Inventors: Christine Hiu-Tung Chen, Zhuoliang Chen, Jorge Garcia Fortanet, Denise Grunenfelder, Rajesh Karki, Mitsunori Kato, Matthew J. LaMarche, Lawrence Blas Perez, Travis Matthew Stams, Sarah Williams
  • Patent number: 11461523
    Abstract: A method for performing glitch power analysis of a circuit, comprising receiving no-timing waveform simulation data for the circuit, the waveform simulation data including a first signal, and identifying a delayed stimulus injection point (DSIP) for the first signal. The method further comprises determining a total delay for the first signal and performing waveform replay simulation including injecting the first signal at the DSIP at a time based on the total delay for the first signal.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: October 4, 2022
    Assignee: Synopsys, Inc.
    Inventors: Chia-Tung Chen, Che-Hua Shih, Shih-Ting Liu, Chia-Chih Yen, Chun Chan, Gung-Yu Pan, Yi-An Chen
  • Patent number: 11401259
    Abstract: The present invention relates to compounds of formula I: in which m, Y1, Y2, Y3, R1, R2a, R2b, R3a, R3b, R4a, R4b, R5a and R5b are defined in the Summary of the Invention; capable of inhibiting the activity of SHP2. The invention further provides a process for the preparation of compounds of the invention, pharmaceutical preparations comprising such compounds and methods of using such compounds and compositions in the management of diseases or disorders associated with the aberrant activity of SHP2.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: August 2, 2022
    Assignee: NOVARTIS AG
    Inventors: Christine Hiu-Tung Chen, Zhuoliang Chen, Jorge Garcia Fortanet, Denise Grunenfelder, Rajesh Karki, Mitsunori Kato, Matthew J. LaMarche, Lawrence Blas Perez, Travis Matthew Stams, Sarah Williams
  • Patent number: 11402743
    Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Ta Lu, Chih-Chiang Tu, Cheng-Ming Lin, Ching-Yueh Chen, Wei-Chung Hu, Ting-Chang Hsu, Yu-Tung Chen
  • Publication number: 20220130729
    Abstract: A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.
    Type: Application
    Filed: January 3, 2022
    Publication date: April 28, 2022
    Inventors: Hung-Hao Chen, Che-Cheng Chang, Horng-Huei Tseng, Wen-Tung Chen, Yu-Cheng Liu
  • Publication number: 20220132042
    Abstract: The embodiments of the disclosure provide a method for tracking a movable object, a tracking device, and a method for controlling shooting parameters of a camera. The method includes: determining a first on duration of a camera of the tracking device, wherein the first on duration comprises a starting time and an ending time; determining a second on duration of a plurality of light emitting elements disposed on the movable object by adding a first guard time before the starting time and adding a second guard time after the ending time; turning on the light emitting elements based on the second on duration; and controlling the camera to capture a specific image of the light emitting elements in the first on duration and accordingly tracking the movable object.
    Type: Application
    Filed: October 21, 2021
    Publication date: April 28, 2022
    Applicant: HTC Corporation
    Inventors: Yuan-Tung Chen, Jyun-Jhong Lin, Chih Chien Chen
  • Patent number: D980210
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: March 7, 2023
    Assignee: Dell Products L.P.
    Inventors: Tung Chen Wu, Yu Weng Alvin Sitoh, Chun Long Goh, Khang Chian Yong, Dong Chul Kang