Abstract: The present invention relates to compounds of formula I: in which p, q, Y1, Y2, R1, R2a, R2b, R3a, R3b, R4a, R4b, R5a, R5b, R7 and R8 are defined in the Summary of the Invention; capable of inhibiting the activity of SHP2. The invention further provides a process for the preparation of compounds of the invention, pharmaceutical preparations comprising such compounds and methods of using such compounds and compositions in the management of diseases or disorders associated with the aberrant activity of SHP2.

Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.

Abstract: The embodiments of the disclosure provide an object tracking method and an object tracking device. The method includes: in a tracking state, controlling an image-capturing device to capture a first image of a specific object, wherein a plurality of light emitting elements are disposed on the specific object, and at least one first light emitting element of the light emitting elements is on and captured in the first image; determining a first object pose of the specific object based on the at least one first light emitting element of the light emitting elements in the first image; obtaining at least one second light emitting element of the light emitting elements based on the first object pose, wherein the at least one second light emitting element is estimated to be uncapturable by the image-capturing device; and turning off the at least one second light emitting element.

Abstract: A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.

Abstract: A method for providing a virtual environment during movement is provided. The method includes the following operations: capturing a first image associated with an interior space of a housing and also associated with part of an external environment captured outward from the interior space; classifying the first image into a first segment associated with the interior space and a second segment associated with the part of the external environment; estimating a first pose and a second pose of a mobile device associated with respective the housing and the external environment, in which the first pose is estimated by a first localization model based on the first segment, and the second pose is estimated by a second localization model based on a second image associated with the external environment; and displaying virtual objects by the mobile device according to the first and second poses.

Abstract: A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.

Abstract: The present invention relates to compounds of formula I: in which p, q, Y1, Y2, R1, R2a, R2b, R3a, R3b, R4a, R4b, R5a, R5b, R7 and R8 are defined in the Summary of the Invention; capable of inhibiting the activity of SHP2. The invention further provides a process for the preparation of compounds of the invention, pharmaceutical preparations comprising such compounds and methods of using such compounds and compositions in the management of diseases or disorders associated with the aberrant activity of SHP2.

Abstract: Disclosures of the present invention mainly describe a two-dimensional semiconductor device (TDSD), comprising: a two-dimensional semiconductor material (TDSM) layer, a superacid action layer and a superacid solution. The TDSM layer is made of a transition-metal dichalcogenide, and the superacid action layer is formed on the TDSM layer. Particularly, an oxide material is adopted for making the superacid action layer, such that the superacid solution is subsequently applied to the superacid action layer so as to make the superacid solution gets into the superacid action layer by diffusion effect. Experimental data have proved that, letting the superacid solution diffuse into the superacid action layer can not only apply a chemical treatment to the TDSM layer, but also make the TDSD have a luminosity enhancement. Particularly, the luminosity enhancement would not be reduced even if the TDSD contacts with water and/or organic solution during other subsequent manufacturing processes.

Abstract: A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.

Abstract: Semiconductor devices and methods of forming the same are provided. A method according to an embodiment includes receiving a substrate including a lower contact feature, depositing a first dielectric layer over a substrate, forming a metal-insulator-metal (MIM) structure over the first dielectric layer, depositing a second dielectric layer over the MIM structure, performing a first etch process to form an opening that extends through the second dielectric layer to expose the MIM structure, performing a second etch process to extend the opening through the MIM structure to expose the first dielectric layer; and performing a third etch process to further extend the opening through the first dielectric layer to expose the lower contact feature. Etchants of the first etch process and the third etch process include fluorine while the etchant of the second etch process is free of fluorine.

Abstract: A two-dimensional (2D) semiconductor with geometry structure and generating method thereof is disclosed herein and the method includes following steps: forming a nano-layer; disposing a 2D material on a substrate; forming a medium layer on the 2D material; transferring the medium layer and the 2D material to the nano-layer; removing the medium layer and leaving the 2D material on a surface of the nano-layer. In accordance with the generating method for 2D semiconductor with geometry structure, a nano microstructure is implemented to enhance and control the 2D materials for field emission and photon emission efficiency.

Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.

Abstract: Semiconductor devices and methods of forming the same are provided. A method according to an embodiment includes receiving a substrate including a lower contact feature, depositing a first dielectric layer over a substrate, forming a metal-insulator-metal (MIM) structure over the first dielectric layer, depositing a second dielectric layer over the MIM structure, performing a first etch process to form an opening that extends through the second dielectric layer to expose the MIM structure, performing a second etch process to extend the opening through the MIM structure to expose the first dielectric layer; and performing a third etch process to further extend the opening through the first dielectric layer to expose the lower contact feature. Etchants of the first etch process and the third etch process include fluorine while the etchant of the second etch process is free of fluorine.

Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.

Abstract: Methods for forming via last through-vias. A method includes providing an active device wafer having a front side including conductive interconnect material disposed in dielectric layers and having an opposing back side; providing a carrier wafer having through vias filled with an oxide extending from a first surface of the carrier wafer to a second surface of the carrier wafer; bonding the front side of the active device wafer to the second surface of the carrier wafer; etching the oxide in the through vias in the carrier wafer to form through oxide vias; and depositing conductor material into the through oxide vias to form conductors that extend to the active carrier wafer and make electrical contact to the conductive interconnect material. An apparatus includes a carrier wafer with through oxide vias extending through the carrier wafer to an active device wafer bonded to the carrier wafer.

Abstract: The present invention relates to compounds of formula I: in which p, q, Y1, Y2, R1, R2a, R2b, R3a, R3b, R4a, R4b, R5a, R5b, R7 and R8 are defined in the Summary of the Invention; capable of inhibiting the activity of SHP2. The invention further provides a process for the preparation of compounds of the invention, pharmaceutical preparations comprising such compounds and methods of using such compounds and compositions in the management of diseases or disorders associated with the aberrant activity of SHP2.

Abstract: Various embodiments of the present disclosure are directed towards a semiconductor structure including a first through substrate via (TSV) within a substrate. The first TSV comprises a first doped region extending from a top surface of the substrate to a bottom surface of the substrate. A conductive via overlies the top surface of the substrate and is electrically coupled to the first TSV.

Abstract: An object tracking method includes following steps: transmitting search information for searching for an object by a first processor during a search stage; receiving the search information and using a second processor to determine whether any of at least one accessory camera has captured an object image in the search stage. When the second processor determines that at least one of the at least one accessory camera has captured the object image, the second processor transmits notification information to the first processor and the first processor enters a tracking stage and transmits request information to the second processor. When the second processor receives the request information, the second processor performs one of the following: transmitting the object image to the first processor, wherein the first processor calculates an object pose according to the object image.

Abstract: A tracking system includes a first device and a second device. The first device includes plural ultrasonic sources and an inertial measurement unit configured to detect inertial data. The second device includes at least one ultrasonic receiver and a processor. The processor is configured to receive the inertial data, estimate an orientation of the first device according to the received inertial data, determine a first ultrasonic transmitter from the ultrasonic transmitters according to the orientation of the first device and a location of the first device, and send an enablement command about the first ultrasonic transmitter to the first device. The enabled transmitter of the ultrasonic transmitters sends ultrasounds according to the enablement command, the at least one ultrasonic receiver is configured to receive the ultrasounds from the first ultrasonic transmitter, and the processor determines the location of the first device according to the received ultrasounds.

Abstract: A backside illuminated image sensor having a photodiode and a first transistor in a sensor region and located in a first substrate, with the first transistor electrically coupled to the photodiode. The image sensor has logic circuits formed in a second substrate. The second substrate is stacked on the first substrate and the logic circuits are coupled to the first transistor through bonding pads, the bonding pads disposed outside of the sensor region.