Abstract: Various embodiments of the present application are directed towards a semiconductor packaging device including a shield structure configured to block magnetic and/or electric fields from a first electronic component and a second electronic component. The first and second electronic components may, for example, be inductors or some other suitable electronic components. In some embodiments, a first IC chip overlies a second IC chip. The first IC chip includes a first substrate and a first interconnect structure overlying the first substrate. The second IC chip includes a second substrate and a second interconnect structure overlying the second substrate. The first and second electronic components are respectively in the first and second interconnect structures. The shield structure is directly between the first and second electronic components.

Abstract: A tracking system includes a first device and a second device. The second device comprises an optical module, an ultrasonic module and a processor. The optical module is configured to capture image data in a first detection field. The ultrasonic module is configured to collect ultrasonic data in a second detection field different from the first detection field. The processor is configured to determine a relative position of a target device relative to the tracking device in a third detection field according to the image data and the ultrasonic data. The third detection field is larger than the first detection field and larger than the second detection field.

Abstract: A method for forming a hybrid-bonding structure is provided. The method includes forming a first dielectric layer over a first semiconductor substrate. The first semiconductor substrate includes a conductive structure. The method also includes partially removing the first dielectric layer to form a first dielectric dummy pattern, a second dielectric dummy pattern and a third dielectric dummy pattern and an opening through the first dielectric layer. The first dielectric dummy pattern, the second dielectric dummy pattern and the third dielectric dummy pattern are surrounded by the opening. In addition, the method includes forming a first conductive line in the opening. The first conductive line is in contact with the conductive structure.

Abstract: Various embodiments of the present disclosure are directed towards an integrated circuit (IC) including a first through substrate via (TSV) within a first semiconductor substrate. The first semiconductor substrate has a front-side surface and a back-side surface respectively on opposite sides of the first semiconductor substrate. The first semiconductor substrate includes a first doped channel region extending from the front-side surface to the back-side surface. The first through substrate via (TSV) is defined at least by the first doped channel region. A first interconnect structure on the front-side surface of the first semiconductor substrate. The first interconnect structure includes a plurality of first conductive wires and a plurality of first conductive vias, and the first conductive wires and the first conductive vias define a conductive path to the first TSV.

Abstract: A method includes depositing a mask layer over a dielectric layer, patterning the mask layer to form a trench, applying a patterned photo resist having a portion over the mask layer, and etching the dielectric layer using the patterned photo resist as an etching mask to form a via opening, which is in a top portion of the dielectric layer. The method further includes removing the patterned photo resist, and etching the dielectric layer to form a trench and a via opening underlying and connected to the trench. The dielectric layer is etched using the mask layer as an additional etching mask. A polymer formed in at least one of the trench and the via opening is removed using nitrogen and argon as a process gas. The trench and the via opening are filled to form a metal line and a via, respectively.

Abstract: The present invention relates to compounds of formula I: in which m, Y1, Y2, Y3, R1, R2a, R2b, R3a, R3b, R4a, R4b, R5a and R5b are defined in the Summary of the Invention; capable of inhibiting the activity of SHP2. The invention further provides a process for the preparation of compounds of the invention, pharmaceutical preparations comprising such compounds and methods of using such compounds and compositions in the management of diseases or disorders associated with the aberrant activity of SHP2.

Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

Abstract: Disclosures of the present invention mainly describe a two-dimensional semiconductor device (TDSD), comprising: a two-dimensional semiconductor material (TDSM) layer, a superacid action layer and a superacid solution. The TDSM layer is made of a transition-metal dichalcogenide, and the superacid action layer is formed on the TDSM layer. Particularly, an oxide material is adopted for making the superacid action layer, such that the superacid solution is subsequently applied to the superacid action layer so as to make the superacid solution gets into the superacid action layer by diffusion effect. Experimental data have proved that, letting the superacid solution diffuse into the superacid action layer can not only apply a chemical treatment to the TDSM layer, but also make the TDSD have a luminosity enhancement. Particularly, the luminosity enhancement would not be reduced even if the TDSD contacts with water and/or organic solution during other subsequent manufacturing processes.

Abstract: A hybrid-bonding structure and a method for forming a hybrid-bonding structure are provided. The hybrid-bonding structure includes a first semiconductor substrate, a first conductive line and a first dielectric dummy pattern. The first conductive line is formed over the first semiconductor substrate. A surface of the first conductive line is configured to hybrid-bond with a second conductive line over a second semiconductor substrate. The first dielectric dummy pattern is formed over the first semiconductor substrate and embedded in the first conductive line.

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

Abstract: The present invention relates to compounds of formula I: in which m, Y1, Y2, Y3, R1, R2a, R2b, R3a, R3b, R4a, R4b, R5a and R5b are defined in the Summary of the Invention; capable of inhibiting the activity of SHP2. The invention further provides a process for the preparation of compounds of the invention, pharmaceutical preparations comprising such compounds and methods of using such compounds and compositions in the management of diseases or disorders associated with the aberrant activity of SHP2.

Abstract: The present disclosure provides a tracking system and method thereof. The tracking system comprises a trackable device with an appearance including a feature pattern and a tracking device. The tracking device comprises an optical sensor module configured to capture a first image which covers the trackable device. The tracking device further comprises a processor coupled to the optical sensor module. The processor is configured to retrieve a region of interest (ROI) of the first image based on the feature pattern, and locate a position of each of a plurality of feature blocks in the ROI, where each feature block contains a portion of the feature pattern. The processor further calculates a pose data of the trackable object according to the positions of the feature blocks.

Abstract: A tracking system is provided. The tracking system comprises a trackable device which comprises a first illuminating module and the first illuminating module emits an infrared (IR) light and a tracking device which comprises an optical sensing module and a processor. The optical module is configured to sense an IR spectrum to capture a first image and sense a visible spectrum to capture a second image, and the IR light is in the IR spectrum. The processor is coupled to the optical sensing module. The processor is configured to search in the first image a first region corresponding to the IR light, locate in the second image a second region associated with the first region in the first image, and calculate a spatial status of the trackable device according to the second region in the second image.

Abstract: An object tracking method includes following steps: transmitting search information for searching for an object by a first processor during a search stage; receiving the search information and using a second processor to determine whether any of at least one accessory camera has captured an object image in the search stage. When the second processor determines that at least one of the at least one accessory camera has captured the object image, the second processor transmits notification information to the first processor and the first processor enters a tracking stage and transmits request information to the second processor. When the second processor receives the request information, the second processor performs one of the following: transmitting the object image to the first processor, wherein the first processor calculates an object pose according to the object image.

Abstract: The present invention relates to compounds of formula I: in which p, q, Y1, Y2, R1, R2a, R2b, R3a, R3b, R4a, R4b, R5a, R5b, R7 and R8 are defined in the Summary of the Invention; capable of inhibiting the activity of SHP2. The invention further provides a process for the preparation of compounds of the invention, pharmaceutical preparations comprising such compounds and methods of using such compounds and compositions in the management of diseases or disorders associated with the aberrant activity of SHP2.

Abstract: A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.

Abstract: A method includes forming a capacitor, which includes depositing a bottom electrode layer, depositing a capacitor insulator layer over the bottom electrode layer, depositing a top electrode layer over the capacitor insulator layer, and depositing a dielectric layer over the top electrode layer. The dielectric layer is etched using a process gas until the top electrode layer is exposed. In the etching of the dielectric layer, the dielectric layer has a first etching rate, and the top electrode layer has a second etching rate, and a ratio of the first etching rate to the second etching rate is higher than about 5.0.

Abstract: A positioning system and method thereof are provided in this disclosure. The positioning method includes steps of: emitting a radiation from a first electronic apparatus to a second electronic apparatus and starting to accumulate a time count; sensing the radiation on the second electronic apparatus and sending a first ultrasonic signal from the second electronic apparatus to the first electronic apparatus; sensing the first ultrasonic signal by a plurality of ultrasound sensors on the first electronic apparatus and calculating a plurality of first time periods started from the radiation is emitted until the first ultrasonic signal is sensed by the ultrasound sensors; calculating a plurality of first relative distances between the ultrasound sensors and a first ultrasound emitter on the second electronic apparatus; and locating a first relative position of the second electronic apparatus relative to the first electronic apparatus according to the first relative distances.

Abstract: A body posture detection system includes an inertial measurement unit, at least two ultrasonic transceivers and a processor. The inertial measurement unit is configured to retrieve an orientation vector of a first portion of a human body. The ultrasonic transceivers are mounted on the first portion and a second portion of the human body respectively. The processor is configured to generate a candidate gesture range of the first portion according to the orientation vector. The processor is configured to measure a distance between the first portion and the second portion according to an ultrasound transmitted between the ultrasonic transceivers. The processor is further configured to determine a current gesture of the first portion from the candidate gesture range according to the distance.