Abstract: A pre-pit signal generating device includes: a first slicer for generating a sliced signal corresponding to a push-pull signal based on a first reference level; a duty ratio controller coupled to the first slicer for adjusting the first reference level or the push-pull signal to control a duty ratio of the sliced signal to a predetermined ratio; a reference level generator coupled to the duty ratio controller for generating a second reference level corresponding to the first reference level; and a second slicer coupled to the reference level generator for generating a first pre-pit signal corresponding to the push-pull signal based on the second reference level.

Abstract: A bisstyryl compound. The bisstyryl compound has formula (I): wherein Z1 and Z2 are benzene, naphthalene, or heterocyclic ring, R1 is H, C1-5 alkyl, hydroxyl, halogen atoms, or alkoxy, R2 is H, halogen atoms, C1-5 alkyl, nitro, ester, carboxyl, sulfo, sulfonamide, sulfuric ester, amide, C1-3 alkoxy, amino, alkylamino, cyano, C1-6 alkylsulfonyl, or C2-7 alkoxy carbonyl, R3, R4, R5, and R6 are H, halogen atoms, alkyl, aralkyl, or heterocyclic ring containing O, S, or N, or R3 and R4 are joined to a nitrogen atom or R5 and R6 are joined together to form a ring, R7 and R8 are H or alkyl, W is nitrogen with or without Z1 and Z2 or aromatic group without Z1 and Z2, Y is carbon, oxygen, sulfur, selenium, —NR, or —C(CH3)2, m is 1-3, n is 1-18, and X1 and X2 are anionic groups or anionic organometallic complexes.

Abstract: A circuit for calibrating the DC offset in a wireless communication device utilizes a voltage-generating circuit to generate a first voltage value and its negative value, and utilizes a detecting circuit to detect an output of the wireless communication device and generate a first target-branch reference value corresponding to the power of the output when the first voltage value is inputted into a target branch (e.g., the in-phase branch or the quadrature branch) of the wireless communication device, and detect an output of the wireless communication device and generate a second target-branch reference value corresponding to the power of the output when the negative value of the first voltage value is input into the target branch. Then, an estimating circuit estimates the DC offset on the target branch according to the first and second target-branch reference values and the first voltage value.

Abstract: A preparation method of a dye incorporated in a recording layer for a high density optical recording medium, having the following general chemical structural formula (I): is provided.

Abstract: The present invention discloses a slope control device capable of predicting uniform-current-sharing level and method thereof which can be applied in a redundancy or distributed power system for providing better uniform-current-sharing ability. The device comprises a high linearity transconductor circuit, a slope adjusting circuit and an incremental output voltage circuit. The invention applies either a transductor parameter or a feedback resistor to increase the droop gain and therefore the current deviation between two power supply modules is reduced. The invention further raises the output voltage step by step to ensure that the output voltage meet the requirement of allowable minimum output voltage according to increment of load current.

Abstract: A flexible electro acoustic actuator with an antenna is provided. The flexible electro acoustic actuator is formed with separate layers of carrier, acoustic oscillation component, intermediate component, and metal electro-conductive component, and characterized by using the metal electro-conductive component to form an antenna transceiver for receiving/sending electromagnetic signals, thereby enabling the flexible electro acoustic actuator to output multimedia sound effects as well as receive/send communication signals.

Abstract: A recording layer including a novel dye for a high density optical recording medium, employing short wavelength laser source with a wavelength no longer than 530 nm 530 nm for recording high density information and reproduction/playback of the high density information recordings, is provided.

Abstract: An integrated circuit system that includes: providing a substrate and a material layer; measuring a parameter of the material layer; and correlating the thickness of an anti-reflective layer to the measured parameter of the material layer for critical dimension control.

Abstract: This invention provides a light-emitting diode chip with high light extraction, which includes a substrate, an epitaxial-layer structure for generating light by electric-optical effect, a transparent reflective layer sandwiched between the substrate and the epitaxial-layer structure, and a pair of electrodes for providing power supply to the epitaxial-layer structure. A bottom surface and top surface of the epitaxial-layer structure are roughened to have a roughness not less than 100 nm root mean square (rms). The light generated by the epitaxial-layer structure is hence effectively extracted out. A transparent reflective layer not more than 5 ?m rms is formed as an interface between the substrate and the epitaxial-layer structure. The light toward the substrate is more effectively reflected upward. The light extraction and brightness are thus enhanced. Methods for manufacturing the light-emitting diode chip of the present invention are also provided.

Abstract: A storage device with self-status detection and an inspection method thereof are provided. The storage device includes a plurality of storage areas (i.e., block tables), a plurality of memory blocks, and a status detection unit. The storage areas respectively have a corresponding weight value, and the addresses of memory blocks which have the same number of error correct codes (ECCs) are recorded in the same storage area. The status detection unit obtains a status of the storage device according to the number of addresses of the memory blocks recorded in a storage area and the corresponding weight value of the storage area.

Abstract: A method for managing a memory block is provided. In this method, a plurality of block tables having different storing priorities is provided. In addition, the number of error correction bits in the memory block is checked. Thereby, in the present invention, data can be stored into the memory block in a block table according to the number of error correction bits in the memory block so that the sequence in which the memory block is used for storing data can be determined.

Abstract: The present invention relates to a memory device and a method of fabricating the same. The memory device comprises a substrate, a tunnel dielectric film on the substrate, pairs of source and drain regions formed in the substrate, and a number of separate storage blocks between each pair of the source and drain regions. Each storage wire block includes a storage medium and a silicon dioxide layer. Two storage blocks are separated by an interval of at least 100 angstroms.

Abstract: For decreasing errors within an analog phase-locked loop, an all-digital phase-locked loop (ADPLL) with digital components and digital operations is used. The ADPLL may also be used for direct frequency modulation (DFM). By defining a proportional path gain of an ADPLL by a bandwidth and a reference frequency of the ADPLL, by a TDC gain, a DCO gain, a dividing ratio of a frequency divider, a gain of an amplifier or a combination thereof, the gain of the amplifier may be adjusted so that an optimal loop bandwidth of the ADPLL may be well calibrated. For achieving the aim of entirely digital of the ADPLL, the gains of the TDC and the DCO may be further adjusted in a digital manner.

Abstract: An error predict code is added into a cycle signal for raising precision of an output signal of a time-to-digital (TDC) decoder. A cyclic TDC (CTDC) is specifically designed within a phase-frequency detector (PFD)/CTDC module of an all-digital phase-locked loop (ADPLL) for enhancing loop bandwidth calibration of the ADPLL. A calibration method is used on the PFD/CTDC module for enhancing the loop bandwidth calibration of the ADPLL as well.

Abstract: Phase error of a time-to-digital converter (TDC) within an all-digital phase-locked loop (ADPLL) is compensated by predicting possible phase error, which are predicted according to an estimated quantization error, a period of a digital-controlled oscillator (DCO), a gain of the TDC or a combination thereof. By appropriate inductions, the possible phase error may be further indicated by the quantization error, a code variance corresponding to a half of a reference period received by a TDC module having the TDC, a dividing ratio of a frequency divider of the ADPLL, a fractional number related to the quantization error o a combination thereof. A digital phase error cancellation module is also used for generating the possible phase error for compensating the phase error of the TDC.

Abstract: This invention provides a light-emitting chip device with high thermal conductivity, which includes an epitaxial chip, an electrode disposed on a top surface of the epitaxial chip and a U-shaped electrode base cooperating with the electrode to provide electric energy to the epitaxial chip for generating light by electric-optical effect. The epitaxial chip includes a substrate and an epitaxial-layer structure with a roughening top surface and a roughening bottom surface for improving light extracted out of the epitaxial chip. A thermal conductive transparent reflective layer is formed between the substrate and the epitaxial-layer structure. The electrode base surrounds the substrate, the transparent reflective layer and a first cladding layer of the epitaxial-layer structure to facilitate the dissipation of the internal waste heat generated when the epitaxial chip emitting light. A method for manufacturing the chip device of the present invention is provided.

Abstract: An automatic power control system, a down sampling circuit and a down sampling method. The automatic power control system is incorporated in an optical disc drive comprising a laser diode for receiving a control signal to generate a laser beam; and a photodetector for detecting the laser beam to generate an analog input signal. The automatic power control system comprises an analog-to-digital converter, a down sampling circuit, a comparator, and a digital-to-analog converter. The analog-to-digital converter converts the analog input signal to digital data. The down sampling circuit, coupled to the analog-to-digital converter, comprises a down sampler, a counter, and a controller. The down sampler receives a predetermined amount of digital data to generate representation data. The counter, coupled to the down sampler, calculates the amount of digital data, and resets the down sampler when the amount equals or exceeds the predetermined count.

Abstract: A method for die attaching is disclosed. At first, at least one die and a die-attach preform are separately provided. The die-attach preform is picked and placed upon a die carrier. Then, the die is picked and placed upon the die-attach preform. The die and the die carrier are heated and clipped, so that the die-attach preform can adhere the die and the die carrier at the same time.

Abstract: A write-protection module for a storage device and the method thereof are disclosed. The write-protection module includes a power supply circuit, a fingerprint sensor, a database, and a microprocessor. The microprocessor for receiving the working power produced by the power supply circuit to maintain operation is respectively coupled to the power supply circuit, the fingerprint sensor, and the database. The fingerprint sensor receives the fingerprint input of a user, and the microprocessor receives the output signal of the fingerprint sensor and converts the output signal into an input cryptograph. Finally, the microprocessor compares the input cryptograph with a predetermined cryptograph stored in the database to produce a comparison information, and determines whether or not the user may access data.

Abstract: A non-volatile memory device, a data access circuit and a data access method are provided. The non-volatile memory device includes a main controller, a plurality of sub-controllers and a plurality of memory blocks. The sub-controllers are coupled to the main controller and are used to execute the tasks assigned by the main controller. The memory blocks are respectively coupled to the corresponding sub-controllers. The main controller is used to divide a received main data into a plurality of sub-data, and the sub-data are respectively saved in the memory blocks through corresponding sub-controllers. Therefore, the data access speed of the non-volatile memory device is substantially speeded-up.