Abstract: A storage bridge includes a flash memory register unit for temporarily storing data and for storing data of a storage unit when a host unit stores data to the storage unit, and a transmission interface control unit coupled to the flash memory register unit for controlling operations of the flash memory register unit.

Abstract: An automatic power control system, a down sampling circuit and a down sampling method. The automatic power control system is incorporated in an optical disc drive comprising a laser diode for receiving a control signal to generate a laser beam; and a photodetector for detecting the laser beam to generate an analog input signal. The automatic power control system comprises an analog-to-digital converter, a down sampling circuit, a comparator, and a digital-to-analog converter. The analog-to-digital converter converts the analog input signal to digital data. The down sampling circuit, coupled to the analog-to-digital converter, comprises a down sampler, a counter, and a controller. The down sampler receives a predetermined amount of digital data to generate representation data. The counter, coupled to the down sampler, calculates the amount of digital data, and resets the down sampler when the amount equals or exceeds the predetermined count.

Abstract: A stocking capable of the convenient holding of articles, wherein the stocking body section extending upward from the sole and along the joint between the calf and the thigh has an additional layer appended to the stocking body in the form of an annular, wrap-around outer layer stocking body. The outer layer stocking body bottom consists of a fixing means disposed at the upper extent of the joint over the sole and an opening at the topmost end that is hemmed. As such, after being worn by the user, articles such as protective equipment and warmth insulating material are directly placed inside the outer layer stocking body and retained in position by the knitted binding force of the outer layer stocking body, thereby enabling effective leg section protection and convenient wearing utility.

Abstract: A method of operating a memory cell by applying a positive voltage to the gate sufficient to cause hole tunneling from the gate toward the charge storage layer is disclosed. The method is applied to a memory cell including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region. The memory cell also has a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer. The upper insulating multi-layer structure comprises a lower dielectric layer and an upper nitride layer disposed above the lower dielectric layer and the memory cell has a gate disposed above the upper insulating multi-layer structure.

Abstract: An electronic device bearing seat includes a casing, a hook, a first resilient element, an ejector, a second resilient element, a pivot, a connecting rod and an ejecting button. The casing has a first opening and a second opening. The hook is movably provided in the first opening and includes a first withstanding post and a recess. The first resilient element is disposed between the casing and the hook. The ejector is movably provided in the second opening and is detachably fastened in the recess. The ejector includes a second withstanding post. The second resilient element is disposed between the casing and the ejector. The shaft is disposed in the casing. The connecting rod is rotatably disposed at and passed by the pivot and pushes against the first and second withstanding post. The ejecting button is movably disposed on the casing and abuts against the connecting rod.

Abstract: The present invention relates to a memory device and a method of fabricating the same. The memory device comprises a substrate, a tunnel dielectric film on the substrate, pairs of source and drain regions formed in the substrate, and a number of separate storage blocks between each pair of the source and drain regions. Each storage wire block includes a storage medium and a silicon dioxide layer. Two storage blocks are separated by an interval of at least 100 angstroms.

Abstract: A method of operating a memory cell by applying a positive voltage to the gate sufficient to cause hole tunneling from the gate toward the charge storage layer is disclosed. The method is applied to a memory cell including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region. The memory cell also has a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer. The upper insulating multi-layer structure comprises a lower dielectric layer and an upper nitride layer disposed above the lower dielectric layer and the memory cell has a gate disposed above the upper insulating multi-layer structure.

Abstract: A constricting device for the footrest ring of a chair includes a constricting unit assembled between the center tube of a chair and the conical sleeve of a footrest ring. The constricting unit consists of a constricting main body and a fixing ring combining the constricting main body and the sleeve of the footrest ring. The constricting main body is a conical body fitted with the conical sleeve of the footrest ring, having its center bored with a fitting hole to be fitted around the center tube of the chair and its circumferential wall cut with plural openings. When the footrest ring is pressed downward by treading, the conical sleeve of the footrest ring will press the conical constricting main body and make it constricted to closely hold the center tube of the chair, able to stably fix the footrest ring on the center tube of the chair.

Abstract: Memory cells including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region; a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer, wherein the upper insulating multi-layer structure comprises a polysilicon material layer interposed between a first dielectric layer and a second dielectric layer; and a gate disposed above the upper insulating multi-layer structure are described along with arrays thereof and methods of operation.

Abstract: Memory cells comprising: a semiconductor substrate having at least two source/drain regions separated by a channel region; a charge-trapping structure disposed above the channel region; and a gate disposed above the charge-trapping structure; wherein the charge-trapping structure comprises a bottom insulating layer, a first charge-trapping layer, and a second charge-trapping layer, wherein an interface between the bottom insulating layer and the substrate has a hydrogen concentration of less than about 3×10/cm?2, and methods for forming such memory cells.

Abstract: A clock rate adjustment apparatus and a method for adjusting a clock rate of a clock for an optical storage system are provided. The clock rate adjustment apparatus comprises an indication provider, a throughput rate detector, and a clock generator. The method performs the following steps. The indication provider generates an indicatory signal indicating a state of the optical storage system. The throughput rate detector generates a control signal in response to the indicatory signal. The clock generator generates the clock at the clock rate in response to the control signal. The clock rate determined by the clock rate adjustment apparatus may be adjusted dynamically in response to a required minimum clock rate and a variable data rate.

Abstract: A manufacturing method of a charge-trapping memory device is provided. This method includes forming a stacked structure having at least a charge-trapping medium. An annealing process in a hydrogen gas is then performed on the stacked structure subsequent to the device fabrication process. The annealing process is conducted at a temperature of about 350° C. to 450° C. and with the concentration of the hydrogen gas greater than 0.5 mole percent.

Abstract: A method for forming a shallow trench isolation region (STI) is disclosed. The method comprises the steps of sequentially forming a pad oxide layer and a nitride silicon layer over a provided substrate. Next, the pad oxide layer, the nitride silicon layer, and the substrate are partially etched to form a trench. An oxide liner and a nitride liner are then formed in the trench. Subsequently, a two-stage high-density plasma chemical vapor deposition process is performed to form a shallow trench isolation region.

Abstract: A method for fabricating a charge trapping memory device includes providing a substrate; forming a first oxide layer on the substrate; forming a number of BD regions in the substrate; nitridizing the interface of the first oxide layer and the substrate via a process; forming a charge trapping layer on the first oxide layer; and forming a second oxide layer on the charge trapping layer.

Abstract: A method for controlling a specific output power level emitted from a laser diode (LD) in an optical pick-up head unit (OPU) is disclosed. The LD is configured to provide a plurality of output power levels for accessing/recording an optical disc. The method includes: determining a specific power control value according to a first output power level, a second output power level, a first power control value of the first output power level, and the specific output power level, wherein the first output power level is less than the specific output power level and greater than the second output power level; and driving the LD to emit the specific output power level according to the specific power control value, the first power control value, and a second power control value of the second output power level.

Abstract: An automatic power control system, a down sampling circuit and a down sampling method. The automatic power control system is incorporated in an optical disc drive comprising a laser diode for receiving a control signal to generate a laser beam; and a photodetector for detecting the laser beam to generate an analog input signal. The automatic power control system comprises an analog-to-digital converter, a down sampling circuit, a comparator, and a digital-to-analog converter. The analog-to-digital converter converts the analog input signal to digital data. The down sampling circuit, coupled to the analog-to-digital converter, comprises a down sampler, a counter, and a controller. The down sampler receives a predetermined amount of digital data to generate representation data. The counter, coupled to the down sampler, calculates the amount of digital data, and resets the down sampler when the amount equals or exceeds the predetermined count.

Abstract: The invention provides an apparatus for demodulating an Address In Pre-groove (ADIP) symbol. The ADIP symbol is carried by a wobble signal of an optical disk and comprises a series of ADIP bits permuted according to one of a plurality of permutation patterns to make up the ADIP symbol. A wobble extraction module extracts the wobble signal from the optical disk. A reference wobble generator generates a reference wobble with the same frequency and phase as a fundamental frequency and phase of a positive wobble cycle of the wobble signal. A waveform difference measurement module then measures a difference between the wobble signal and the reference wobble to obtain a series of difference measurement values respectively corresponding to the ADIP bits. A pattern matching module then compares probabilities of the permutation of the ADIP bits agreeing with each of the permutation patterns according to the difference measurement values to determine the ADIP symbol.

Abstract: The invention provides a wobble detection circuit. An exemplary embodiment of the wobble detection circuit comprises an automatic gain control module, an analog to digital converter, a digital band pass filter, and a digital band pass filter. The automatic gain control module amplifies a first input signal and a second input signal detected by a pickup head to the same magnitude to obtain a first amplified signal and a second amplified signal. The adder then subtracts the second amplified signal from the first amplified signal to obtain an analog wobble signal. The analog to digital converter then converts the analog wobble signal to a first digital wobble signal. Finally, the digital band pass filter accepts frequency components of the first digital wobble signal within a pass band and rejects frequency components of the first digital wobble signal outside the pass band to obtain a second digital wobble signal.

Abstract: An apparatus for detecting the wobble carrier frequency of an optical disk is disclosed. The apparatus comprises an offset canceller, a binary conversion module, an adjustable band pass filter, and a frequency detection module. The offset canceller cancels the direct current offset of a first wobble signal to obtain a second wobble signal. The binary conversion module converts the second wobble signal to a binary data stream. The adjustable band pass filter passes only an adjustable frequency range of the binary data stream to generate a filtered signal, wherein the center frequency of the adjustable frequency range is sequentially adjusted. The frequency detection module then determines maximum amplitude of the filtered signal, and determines the center frequency of the adjustable frequency range according to which the filtered signal with the maximum amplitude is generated, wherein the wobble carrier frequency is the center frequency corresponding to the maximum amplitude.

Abstract: The invention provides an automatic gain controller processing an input signal for wobble detection circuit. An exemplary embodiment of the automatic gain controller comprises an envelope detection module, an analog to digital converter, a digital control module, a digital to analog converter, and a variable gain amplifier. The envelope detection module detects an envelope magnitude of an amplified signal. The analog to digital converter converts the envelope magnitude from analog to digital to obtain a digital envelope signal. The digital control module determines a digital gain signal for amplification of the input signal according to the digital envelope signal. The digital to analog converter converts the digital gain signal to an analog gain signal. The variable gain amplifier then amplifies the input signal according to the analog gain signal to obtain the amplified wobble signal.