Patents by Inventor Anand S

Anand S has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10008250
    Abstract: Methods and apparatus related to cost optimized Single Level Cell (SLC) write buffering for Three Level Cell (TLC) Solid State Drives (SSDs) are described. In one embodiment, non-volatile memory includes a first region in a Single Level Cell (SLC) mode and a second region in a multiple level cell mode. A portion of the second region is moved from the multiple level cell mode to the SLC mode, without adding any new capacity to the non-volatile memory and without reducing any existing capacity from the non-volatile memory.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 26, 2018
    Assignee: Intel Corporation
    Inventor: Anand S. Ramalingam
  • Patent number: 10009117
    Abstract: Data can be transferred from one device to another in the Internet of Things without using a network by a touch-based human body communication (HBC) interaction between a wearable storage module and HBC-compatible interface pads on external host devices. Information on a source host device is copied to the wearable storage module when the user touches the source device's HBC interface pad, can be stored indefinitely on the wearable module, and is copied to a destination host device when the user touches the destination devices HBC interface pad. Because the interface pads only need to be simple electrodes, their size and shape can be widely varied to fit the host devices.
    Type: Grant
    Filed: December 26, 2014
    Date of Patent: June 26, 2018
    Assignee: Intel Corporation
    Inventors: Jaroslaw J. Sydir, Anand S. Konanur, Ulun Karacaoglu, Anthony G. LaMarca, Stephen R. Wood
  • Publication number: 20180173418
    Abstract: Provided are an apparatus, system and method for offloading collision check operations in a memory storage device to a collision check unit. A collision check unit includes a collision table including logical addresses for pending Input/Output (I/O) requests. An I/O request is received to a target logical address addressing a block of data in the non-volatile memory. The logical address is sent to the collision check unit. Resources to transfer data with respect to the transfer buffer to data for the I/O request are allocated in parallel while the collision check unit is determining whether the collision table includes the target logical address. The collision check unit determines whether the collision table includes the target logical address and returns indication of whether the collision table includes the target logical address indicating that current data for the target logical address is already in the transfer buffer.
    Type: Application
    Filed: December 20, 2016
    Publication date: June 21, 2018
    Inventors: Peng LI, Anand S. RAMALINGAM, Jawad B. KHAN, William K. LUI, Divya NARAYANAN, Sanjeev N. TRIKA
  • Patent number: 9996496
    Abstract: Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: June 12, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Doyle Rivers, Paul D. Ruby, Anand S. Ramalingam, Rajesh Sundaram, Julie M. Walker
  • Patent number: 9997414
    Abstract: Techniques are disclosed for forming Ge/SiGe-channel and III-V-channel transistors on the same die. The techniques include depositing a pseudo-substrate of Ge/SiGe or III-V material on a Si or insulator substrate. The pseudo-substrate can then be patterned into fins and a subset of the fins can be replaced by the other of Ge/SiGe or III-V material. The Ge/SiGe fins can be used for p-MOS transistors and the III-V material fins can be used for n-MOS transistors, and both sets of fins can be used for CMOS devices, for example. In some instances, only the channel region of the subset of fins are replaced during, for example, a replacement gate process. In some instances, some or all of the fins may be formed into or replaced by one or more nanowires or nanoribbons.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: June 12, 2018
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Karthik Jambunathan
  • Publication number: 20180158927
    Abstract: A non-planar gate all-around device and method of fabrication thereby are described. In one embodiment, a multi-layer stack is formed by selectively depositing the entire epi-stack in an STI trench. The channel layer is grown pseudomorphically over a buffer layer. A cap layer is grown on top of the channel layer. In an embodiment, the height of the STI layer remains higher than the channel layer until the formation of the gate. A gate dielectric layer is formed on and all-around each channel nanowire. A gate electrode is formed on the gate dielectric layer and surrounding the channel nanowire.
    Type: Application
    Filed: June 26, 2015
    Publication date: June 7, 2018
    Inventors: Chandra S. MOHAPATRA, Anand S. MURTHY, Glenn A. GLASS, Willy RACHMADY, Gilbert DEWEY, Jack T. KAVALIEROS, Tahir GHANI, Matthew V. METZ
  • Publication number: 20180158957
    Abstract: Crystalline heterostructures including an elevated fin structure extending from a sub-fin structure over a substrate. Devices, such as III-V transistors, may be formed on the raised fin structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate. A sub-fin isolation material localized to a transistor channel region of the fin structure may reduce source-to-drain leakage through the sub-fin, improving electrical isolation between source and drain ends of the fin structure. Subsequent to heteroepitaxially forming the fin structure, a portion of the sub-fin may be laterally etched to undercut the fin. The undercut is backfilled with sub-fin isolation material. A gate stack is formed over the fin. Formation of the sub-fin isolation material may be integrated into a self-aligned gate stack replacement process.
    Type: Application
    Filed: June 26, 2015
    Publication date: June 7, 2018
    Inventors: Willy RACHMADY, Matthew V. METZ, Gilbert DEWEY, Chandra S. MOHAPATRA, Jack T. KAVALIEROS, Anand S. MURTHY, Tahir GHANI, Nadia M. RAHHAL-ORABI, Sanaz K. GARDNER
  • Publication number: 20180158958
    Abstract: Transistor devices may be formed having a buffer between an active channel and a substrate, wherein the active channel and a portion of the buffer form a gated region. The active channel may comprise a low band-gap material on a sub-structure, e.g. the buffer, between the active channel and the substrate. The sub-structure may comprise a high band-gap material having a desired conduction band offset, such that leakage may be arrested without significant impact on electron mobility within the active channel. In an embodiment, the active channel and the sub-structure may be formed in a narrow trench, such that defects due to lattice mismatch between the active channel and the sub-structure are terminated in the sub-structure.
    Type: Application
    Filed: May 27, 2015
    Publication date: June 7, 2018
    Inventors: Chandra S. Mohapatra, Gilbert Dewey, Anand S. Murthy, Glenn A. Glass, Willy Rachmady, Jack T. Kavalieros, Tahir Ghani, Matthew V. Metz
  • Publication number: 20180158944
    Abstract: Techniques are disclosed for forming high mobility NMOS fin-based transistors having an indium-rich channel region electrically isolated from the sub-fin by an aluminum-containing layer. The aluminum aluminum-containing layer may be provisioned within an indium-containing layer that includes the indium-rich channel region, or may be provisioned between the indium-containing layer and the sub-fin. The indium concentration of the indium-containing layer may be graded from an indium-poor concentration near the aluminum-containing barrier layer to an indium-rich concentration at the indium-rich channel layer. The indium-rich channel layer is at or otherwise proximate to the top of the fin, according to some example embodiments. The grading can be intentional and/or due to the effect of reorganization of atoms at the interface of indium-rich channel layer and the aluminum-containing barrier layer. Numerous variations and embodiments will be appreciated in light of this disclosure.
    Type: Application
    Filed: June 23, 2015
    Publication date: June 7, 2018
    Applicant: INTEL CORPORATION
    Inventors: CHANDRA S. MOHAPATRA, ANAND S. MURTHY, GLENN A. GLASS, TAHIR GHANI, WILLY RACHMADY, JACK T. KAVALIEROS, GILBERT DEWEY, MATTHEW V. METZ, HAROLD W. KENNEL
  • Publication number: 20180158737
    Abstract: A method including forming a fin of a nonplanar device on a substrate, the fin including a second layer between a first layer and a third layer; replacing the second layer with a dielectric material; and forming a gate stack on a channel region of the fin. An apparatus including a first multigate device on a substrate including a fin including a conducting layer on a dielectric layer, a gate stack disposed on the conducting layer in a channel region of the fin, and a source and a drain formed in the fin, and a second multigate device on the substrate including a fin including a first conducting layer and a second conducting layer separated by a dielectric layer, a gate stack disposed the first conducting layer and the second conducting layer in a channel region of the fin, and a source and a drain formed in the fin.
    Type: Application
    Filed: June 27, 2015
    Publication date: June 7, 2018
    Inventors: Seiyon KIM, Jack T. KAVALIEROS, Anand S. MURTHY, Glenn A. GLASS, Karthik JAMBUNATHAN
  • Publication number: 20180158841
    Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. In accordance with an embodiment, sacrificial fins are cladded and then removed thereby leaving the cladding layer as a pair of standalone fins. Once the sacrificial fin areas are filled back in with a suitable insulator, the resulting structure is fin-on-insulator. The new fins can be configured with any materials by using such a cladding-on-core approach. The resulting fin-on-insulator structure is favorable, for instance, for good gate control while eliminating or otherwise reducing sub-channel source-to-drain (or drain-to-source) leakage current. In addition, parasitic capacitance from channel-to-substrate is significantly reduced.
    Type: Application
    Filed: June 26, 2015
    Publication date: June 7, 2018
    Applicant: INTEL CORPORATION
    Inventors: GLENN A. GLASS, ANAND S. MURTHY, DANIEL B. AUBERTINE, TAHIR GHANI, JACK T. KAVALIEROS, BENJAMIN CHU-KUNG, CHANDRA S. MOHAPATRA, KARTHIK JAMBUNATHAN, GILBERT DEWEY, WILLY RACHMADY
  • Publication number: 20180151732
    Abstract: Techniques are disclosed for resistance reduction in p-MOS transistors having epitaxially grown boron-doped silicon germanium (SiGe:B) S/D regions. The techniques can include growing one or more interface layers between a silicon (Si) channel region of the transistor and the SiGe:B replacement S/D regions. The one or more interface layers may include: a single layer of boron-doped Si (Si:B); a single layer of SiGe:B, where the Ge content in the interface layer is less than that in the resulting SiGe:B S/D regions; a graded layer of SiGe:B, where the Ge content in the alloy starts at a low percentage (or 0%) and is increased to a higher percentage; or multiple stepped layers of SiGe:B, where the Ge content in the alloy starts at a low percentage (or 0%) and is increased to a higher percentage at each step. Inclusion of the interface layer(s) reduces resistance for on-state current flow.
    Type: Application
    Filed: June 19, 2015
    Publication date: May 31, 2018
    Applicant: INTEL CORPORATION
    Inventors: RISHABH MEHANDRU, ANAND S. MURTHY, TAHIR GHANI, GLENN A. GLASS, KARTHIK JAMBUNATHAN, SEAN T. MA, CORY E. WEBER
  • Publication number: 20180151733
    Abstract: Techniques are disclosed for forming p-MOS transistors having one or more carbon-based interface layers between epitaxially grown S/D regions and the channel region. In some cases, the carbon-based interface layer(s) may comprise a single layer having a carbon content of greater than 20% carbon and a thickness of 0.5-8 nm. In some cases, the carbon-based interface layer(s) may comprise a single layer having a carbon content of less than 5% and a thickness of 2-10 nm. In some such cases, the single layer may also comprise boron-doped silicon (Si:B) or boron-doped silicon germanium (SiGe:B). In some cases, one or more additional interface layers may be deposited on the carbon-based interface layer(s), where the additional interface layer(s) comprises Si:B and/or SiGe:B. The techniques can be used to improve short channel effects and improve the effective gate length of a resulting transistor.
    Type: Application
    Filed: June 19, 2015
    Publication date: May 31, 2018
    Applicant: INTEL CORPORATION
    Inventors: GLENN A. GLASS, PATRICK H. KEYS, HAROLD W. KENNEL, RISHABH MEHANDRU, ANAND S. MURTHY, KARTHIK JAMBUNATHAN
  • Publication number: 20180151702
    Abstract: A method including forming a non-planar conducting channel of a multi-gate device on a substrate, the channel including a height dimension defined from a base at a surface of the substrate; modifying less than an entire portion of the channel; and forming a gate stack on the channel, the gate stack including a dielectric material and a gate electrode. An apparatus including a non-planar multi-gate device on a substrate including a channel including a height dimension defining a conducting portion and an oxidized portion and a gate stack disposed on the channel, the gate stack including a dielectric material and a gate electrode.
    Type: Application
    Filed: June 27, 2015
    Publication date: May 31, 2018
    Inventors: Seiyon KIM, Gopinath BHIMARASETTI, Rafael RIOS, Jack T. KAVALIEROS, Tahir GHANI, Anand S. MURTHY, Rishabh MEHANDRU
  • Publication number: 20180151677
    Abstract: Techniques are disclosed for reducing off-state leakage of fin-based transistors through the use of a sub-fin passivation layer. In some cases, the techniques include forming sacrificial fins in a bulk silicon substrate and depositing and planarizing shallow trench isolation (STI) material, removing and replacing the sacrificial silicon fins with a replacement material (e.g., SiGe or III-V material), removing at least a portion of the STI material to expose the sub-fin areas of the replacement fins, applying a passivating layer/treatment/agent to the exposed sub-fins, and re-depositing and planarizing additional STI material. Standard transistor forming processes can then be carried out to complete the transistor device. The techniques generally provide the ability to add arbitrary passivation layers for structures that are grown in STI-based trenches. The passivation layer inhibits sub-fin source-to-drain (and drain-to-source) current leakage.
    Type: Application
    Filed: June 24, 2015
    Publication date: May 31, 2018
    Applicant: INTEL CORPORATION
    Inventors: GLENN A. GLASS, YING PANG, ANAND S. MURTHY, TAHIR GHANI, KARTHIK JAMBUNATHAN
  • Patent number: 9985958
    Abstract: Apparatus, methods, and systems described herein are for segmentation, handshaking, and access control solutions for Opendots technology. One embodiment described a charging pad that includes a plurality of conductive strips, switches, and decipher circuitry. A switch is coupled to the plurality of conductive strips whereas the decipher circuitry is coupled to the plurality of conductive strips and the switch. In response to contact with one conductive strip of the plurality of conductive strips, the decipher circuitry determines whether a security password has been received. The switch allows a voltage higher than a threshold voltage level to be supplied to an external device if the security password is received by the decipher circuitry. However, the switch can also prevent a voltage higher than a threshold voltage level to be supplied to an external device if the security password is not received by the decipher circuitry.
    Type: Grant
    Filed: March 26, 2016
    Date of Patent: May 29, 2018
    Assignee: Intel Corporation
    Inventors: Bo Qiu, Jianfang Zhu, Anand S. Konanur, Bradley A. Jackson, Sayan Lahiri
  • Publication number: 20180145077
    Abstract: Monolithic FETs including a majority carrier channel in a first high carrier mobility semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a lateral channel region, a spacer of a high carrier mobility semiconductor material is overgrown, for example wrapping around a dielectric lateral spacer, to increase effective spacing between the transistor source and drain without a concomitant increase in transistor footprint. Source/drain regions couple electrically to the lateral channel region through the high-mobility semiconductor spacer, which may be substantially undoped (i.e. intrinsic). With effective channel length for a given lateral gate dimension increased, the transistor footprint for a given off-state leakage may be reduced or off-state source/drain leakage for a given transistor footprint may be reduced, for example.
    Type: Application
    Filed: June 26, 2015
    Publication date: May 24, 2018
    Inventors: Gilbert DEWEY, Matthew V. METZ, Anand S. MURTHY, Tahir GHANI, Willy RACHMADY, Chandra S. MOHAPATRA, Jack T. KAVALIEROS, Glenn A. GLASS
  • Publication number: 20180145174
    Abstract: Techniques are disclosed for improved integration of germanium (Ge)-rich p-MOS source/drain contacts to, for example, reduce contact resistance. The techniques include depositing the p-type Ge-rich layer directly on a silicon (Si) surface in the contact trench location, because Si surfaces are favorable for deposition of high quality conductive Ge-rich materials. In one example method, the Ge-rich layer is deposited on a surface of the Si substrate in the source/drain contact trench locations, after removing a sacrificial silicon germanium (SiGe) layer previously deposited in the source/drain locations. In another example method, the Ge-rich layer is deposited on a Si cladding layer in the contact trench locations, where the Si cladding layer is deposited on a functional p-type SiGe layer. In some cases, the Ge-rich layer comprises at least 50% Ge (and may contain tin (Sn) and/or Si) and is boron (B) doped at levels above 1E20 cm?3.
    Type: Application
    Filed: January 2, 2018
    Publication date: May 24, 2018
    Applicant: INTEL CORPORATION
    Inventors: GLENN A. GLASS, ANAND S. MURTHY, TAHIR GHANI, YING PANG, NABIL G. MISTKAWI
  • Publication number: 20180130801
    Abstract: Non-silicon fin structures extend from a crystalline heteroepitaxial well material in a well recess of a substrate. III-V finFETs may be formed on the fin structures within the well recess while group IV finFETs are formed in a region of the substrate adjacent to the well recess. The well material may be electrically isolated from the substrate by an amorphous isolation material surrounding pillars passing through the isolation material that couple the well material to a seeding surface of the substrate and trap crystal growth defects. The pillars may be expanded over the well-isolation material by lateral epitaxial overgrowth, and the well recess filled with a single crystal of high quality. Well material may be planarized with adjacent substrate regions. N-type fin structures may be fabricated from the well material in succession with p-type fin structures fabricated from the substrate, or second epitaxial well.
    Type: Application
    Filed: June 26, 2015
    Publication date: May 10, 2018
    Inventors: Willy Rachmady, Matthew V. Metz, Gilbert Dewey, Chandra S. Mohapatra, Jack T. Kavalieros, Anand S. Murthy, Nadia M. Rahhal-Orabi, Tahir Ghani
  • Patent number: 9966440
    Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a metal contact such as one or more metals/alloys on silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example embodiment, an intermediate tin doped III-V material layer is provided between the source/drain and contact metal to significantly reduce contact resistance. Partial or complete oxidation of the tin doped layer can be used to further improve contact resistance. In some example cases, the tin doped III-V material layer has a semiconducting phase near the substrate and an oxide phase near the metal contact. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs, nanowire transistors, etc), as well as strained and unstrained channel structures.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: May 8, 2018
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Michael J. Jackson, Harold W. Kennel