Patents by Inventor Anand S

Anand S has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170229543
    Abstract: Transistor devices having indium gallium arsenide active channels, and processes for the fabrication of the same, that enables improved carrier mobility when fabricating fin shaped active channels, such as those used in tri-gate or gate all around (GAA) devices. In one embodiment, an indium gallium arsenide material may be deposited in narrow trenches which may result in a fin that has indium rich surfaces and a gallium rich central portion. These indium rich surfaces will abut a gate oxide of a transistor and may result in high electron mobility and an improved switching speed relative to conventional homogeneous composition indium gallium arsenide active channels.
    Type: Application
    Filed: September 19, 2014
    Publication date: August 10, 2017
    Applicant: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Chandra S. Mohapatra, Tahir Ghani, Willy Rachmady, Gilbert Dewey, Matthew V. Metz, Jack T. Kavalieros
  • Publication number: 20170229342
    Abstract: Techniques are disclosed for transistor fabrication including a sacrificial protective layer for source/drain (S/D) regions to minimize contact resistance. The sacrificial protective layer may be selectively deposited on S/D regions after such regions have been formed, but prior to the deposition of an insulator layer on the S/D regions. Subsequently, after contact trench etch is performed, an additional etch process may be performed to remove the sacrificial protective layer and expose a clean S/D surface. Thus, the sacrificial protective layer can protect the contact locations of the S/D regions from contamination (e.g., oxidation or nitridation) caused by insulator layer deposition. The sacrificial protective layer can also protect the S/D regions from undesired insulator material remaining on the S/D contact surface, particularly for non-planar transistor structures (e.g., finned or nanowire/nanoribbon transistor structures).
    Type: Application
    Filed: April 24, 2017
    Publication date: August 10, 2017
    Applicant: INTEL CORPORATION
    Inventors: GLENN A. GLASS, ANAND S. MURTHY, MICHAEL J. JACKSON, MICHAEL L. HATTENDORF, SUBHASH M. JOSHI
  • Patent number: 9728464
    Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: August 8, 2017
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Daniel B. Aubertine, Anand S. Murthy, Gaurav Thareja, Tahir Ghani
  • Publication number: 20170221724
    Abstract: Techniques are disclosed for forming transistor devices having source and drain regions with high concentrations of boron doped germanium. In some embodiments, an in situ boron doped germanium, or alternatively, boron doped silicon germanium capped with a heavily boron doped germanium layer, are provided using selective epitaxial deposition in the source and drain regions and their corresponding tip regions. In some such cases, germanium concentration can be, for example, in excess of 50 atomic % and up to 100 atomic %, and the boron concentration can be, for instance, in excess of 1E20 cm?3. A buffer providing graded germanium and/or boron concentrations can be used to better interface disparate layers. The concentration of boron doped in the germanium at the epi-metal interface effectively lowers parasitic resistance without degrading tip abruptness. The techniques can be embodied, for instance, in planar or non-planar transistor devices.
    Type: Application
    Filed: April 17, 2017
    Publication date: August 3, 2017
    Applicant: INTEL CORPORATION
    Inventors: ANAND S. MURTHY, GLENN A. GLASS, TAHIR GHANI, RAVI PILLARISETTY, NILOY MUKHERJEE, JACK T. KAVALIEROS, ROZA KOTLYAR, WILLY RACHMADY, MARK Y. LIU
  • Publication number: 20170222052
    Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.
    Type: Application
    Filed: April 17, 2017
    Publication date: August 3, 2017
    Applicant: Intel Corporation
    Inventors: Cory E. Weber, Mark Y. Liu, Anand S. Murthy, Hemant V. Deshpande, Daniel B. Aubertine
  • Publication number: 20170222035
    Abstract: Transistor fin elements (e.g., fin or tri gate) may be modified by radio frequency (RF) plasma and/or thermal processing for purpose of dimensional sculpting. The etched, thinned fins may be formed by first forming wider single crystal fins, and after depositing trench oxide material between the wider fins, etching the wider fins using a second etch to form narrower single crystal fins having undamaged top and sidewalls for epitaxially growing active channel material. The second etch may remove a thickness of between a 1 nm and 15 nm of the top surfaces and the sidewalls of the wider fins. It may remove the thickness using (1) chlorine or fluorine based chemistry using low ion energy plasma processing, or (2) low temperature thermal processing that does not damage fins via energetic ion bombardment, oxidation or by leaving behind etch residue that could disrupt the epitaxial growth quality of the second material.
    Type: Application
    Filed: April 13, 2017
    Publication date: August 3, 2017
    Inventors: Glenn A. GLASS, Anand S. MURTHY, Daniel B. AUBERTINE, Subhash M. JOSHI
  • Patent number: 9722460
    Abstract: Described herein are techniques related to near field coupling (e.g., wireless power transfers (WPF) and near field communications (NFC)) operations among others. This Abstract is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: Songnan Yang, Emily B. Cooper, Jim J. Walsh, Anand S. Konanur
  • Patent number: 9722023
    Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 1, 2017
    Assignee: Intel Corporation
    Inventors: Glenn A. Glass, Anand S. Murthy, Tahir Ghani
  • Publication number: 20170201105
    Abstract: Apparatus, methods, and systems are herein described for segmentation, handshaking, and access control solutions for Opendots technology. The present disclosure provides a charging pad that includes a plurality of conductive strips, switches, and decipher circuitry. A switch may be coupled to the conductive strips whereas the decipher circuitry may be coupled to the conductive strips and the switch. In response to contact with one of the conductive strips, the decipher circuitry determines whether a security password has been received. The switch allows a voltage higher than a threshold voltage level to be supplied to an external device if the security password is received by the decipher circuitry. However, the switch may also prevent a voltage higher than a threshold voltage level to be supplied to an external device if the security password is not received by the decipher circuitry.
    Type: Application
    Filed: March 26, 2016
    Publication date: July 13, 2017
    Inventors: Bo Qiu, Jianfang Zhu, Anand S. Konanur, Bradley A. Jackson, Sayan Lahiri
  • Patent number: 9705000
    Abstract: Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. In some example embodiments, the techniques can be used to implement the contacts of MOS transistors of a CMOS device, where an intermediate III-V semiconductor material layer is provided between the p-type and n-type source/drain regions and their respective contact metals to significantly reduce contact resistance. The intermediate III-V semiconductor material layer may have a small bandgap (e.g., lower than 0.5 eV) and/or otherwise be doped to provide the desired conductivity. The techniques can be used on numerous transistor architectures (e.g., planar, finned, and nanowire transistors), including strained and unstrained channel structures.
    Type: Grant
    Filed: July 18, 2016
    Date of Patent: July 11, 2017
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy, Tahir Ghani
  • Patent number: 9705187
    Abstract: This document discloses one or more systems, apparatuses, methods, etc. for integrating coil antennas in a carbon fiber chassis portable device. More particularly, the carbon fiber chassis portable device containing unidirectional weave carbon fibers in its chassis—to support near field communications (NFC) related functions—is described.
    Type: Grant
    Filed: February 1, 2016
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventors: Anand S. Konanur, Ulun Karacaoglu
  • Patent number: 9704003
    Abstract: Control of an apparatus is provided according to determination of positioning of information pieces with radio frequency identification (RFID) tags. In embodiments, an apparatus may include one or more pieces, wherein each piece may be positionable in one or more piece positions of a region and may include a passive RFID tag that stores information relating to a characteristic of the piece. An arrangement of RFID antennas may be positioned proximal to the region, and a RFID reader may provide reads of the pieces near the RFID antennas. One or more processors may determine the piece positions of the one or more pieces from the reads and may provide control of the apparatus according to the one or more pieces and their piece positions.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventors: Glen J. Anderson, Anand S. Konanur, Kevin W. Bross, Gregory A. Peek, Rebecca A. Chierichetti, Ankur Agrawal
  • Publication number: 20170186855
    Abstract: Microelectronic structures embodying the present invention include a field effect transistor (FET) having highly conductive source/drain extensions. Formation of such highly conductive source/drain extensions includes forming a passivated recess which is back filled by epitaxial deposition of doped material to form the source/drain junctions. The recesses include a laterally extending region that underlies a portion of the gate structure. Such a lateral extension may underlie a sidewall spacer adjacent to the vertical sidewalls of the gate electrode, or may extend further into the channel portion of a FET such that the lateral recess underlies the gate electrode portion of the gate structure. In one embodiment the recess is back filled by an in-situ epitaxial deposition of a bilayer of oppositely doped material. In this way, a very abrupt junction is achieved that provides a relatively low resistance source/drain extension and further provides good off-state subthreshold leakage characteristics.
    Type: Application
    Filed: March 16, 2017
    Publication date: June 29, 2017
    Inventors: Anand S. Murthy, Robert S. CHAU, Patrick MORROW, Chia-Hong JAN, Paul PACKAN
  • Publication number: 20170187221
    Abstract: A method of wirelessly charging batteries of devices includes detecting at least two devices being simultaneously present on a charging mat. It is determined, for each of the at least two devices, whether the device is compatible with a wireless charging standard. It is determined, for each of the two devices, whether the device is enabled for a near field communication. Charging of the devices is prevented if at least one of the devices is enabled for a near field communication but not compatible with the wireless charging standard.
    Type: Application
    Filed: December 24, 2015
    Publication date: June 29, 2017
    Applicant: Intel Corproation
    Inventors: Anand S. Konanur, Lei Shao, Steven G. Gaskill, Xintian E. Lin, Songnan Yang, Jason Ku, Jie Gao
  • Patent number: 9692525
    Abstract: Described herein are architectures, platforms and methods for enhancing human body communications (HBC) mode during near field communication (NFC) related functions or transactions. Optimization of the HBC communications system can include a radio frequency (RF) tuning circuitry to generate a voltage-based resonant frequency at respective capacitive pads of transmitting and receiving devices. The RF tuning circuitry includes a series connected capacitor-inductor driver that may be constructed within or outside of an NFC module circuitry or NFC silicon.
    Type: Grant
    Filed: June 25, 2015
    Date of Patent: June 27, 2017
    Assignee: Intel Corporation
    Inventors: Anand S. Konanur, Niranjan Karandikar
  • Publication number: 20170177243
    Abstract: Technologies for performing a data copy operation on a data storage device include storing a copy token in a power-fail-safe data structure that identifies the source address and destination address of the data copy operation, updating an address table to indicate that the source and destination addresses are involved in the data copy operation, and notifying a host requesting that data copy operation that the data copy operation has been completed prior to performing the data copy operation. The host may subsequently perform other tasks while the data storage device completes the data copy operation. During the data copy operation, data access requests to the source or destination addresses are blocked based on the address table. Additionally, should a power failure event occur, the power-fail-safe data structure is saved to non-volatile data storage so that the copy operation may be completed upon the next power-on event of the data storage device.
    Type: Application
    Filed: December 18, 2015
    Publication date: June 22, 2017
    Inventors: Sanjeev N. Trika, Anand S. Ramalingam
  • Publication number: 20170179573
    Abstract: Described herein are techniques related to near field coupling and WLAN dual-band operations. For example, a WLAN dual-band utilizes the same coil antenna that is utilized for near field communications (NFC) functions. The WLAN dual-band may be integrated into an NFC module to form a single module.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 22, 2017
    Inventors: Anand S. Konanur, Ulun Karacaoglu, Songnan Yang
  • Publication number: 20170162447
    Abstract: Techniques are disclosed for forming Ge/SiGe-channel and III-V-channel transistors on the same die. The techniques include depositing a pseudo-substrate of Ge/SiGe or III-V material on a Si or insulator substrate. The pseudo-substrate can then be patterned into fins and a subset of the fins can be replaced by the other of Ge/SiGe or III-V material. The Ge/SiGe fins can be used for p-MOS transistors and the III-V material fins can be used for n-MOS transistors, and both sets of fins can be used for CMOS devices, for example. In some instances, only the channel region of the subset of fins are replaced during, for example, a replacement gate process. In some instances, some or all of the fins may be formed into or replaced by one or more nanowires or nanoribbons.
    Type: Application
    Filed: June 24, 2014
    Publication date: June 8, 2017
    Applicant: INTEL CORPORATION
    Inventors: GLENN A. GLASS, ANAND S. MURTHY, KARTHIK JAMBUNATHAN
  • Patent number: 9660704
    Abstract: Described herein are techniques related one or more systems, apparatuses, methods, etc. for reducing induced currents in a apparatus chassis. For example, a fractal slot is constructed in the apparatus chassis to reduce the induced currents, and enhance passage of magnetic fields through the apparatus chassis. In this example, the fractal slot may include a no-self loop fractal space filling curve shape to provide high impedance to the induced currents.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: May 23, 2017
    Assignee: Intel IP Corporation
    Inventors: Anand S. Konanur, Ulun Karacaoglu, Songnan Yang
  • Patent number: 9661446
    Abstract: Described herein are techniques related to near field coupling and WLAN dual-band operations. For example, a WLAN dual-band utilizes the same coil antenna that is utilized for near field communications (NFC) functions. The WLAN dual-band may be integrated into an NFC module to form a single module.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: May 23, 2017
    Assignee: Intel Corporation
    Inventors: Anand S. Konanur, Ulun Karacaoglu, Songnan Yang