Patents by Inventor Anand S

Anand S has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180121092
    Abstract: A controller of a solid state drive initiates a repacking of data stored in a non-volatile memory of the solid state drive, wherein refreshing of the data stored in the non-volatile memory of the solid state drive is performed during the repacking of the data stored in the non-volatile memory of the solid state drive. Logical blocks are placed physically contiguously in an increasing order in pre-erased locations of the non-volatile memory of the solid state drive while the data stored in the non-volatile memory of the solid state drive is being repacked.
    Type: Application
    Filed: October 2, 2017
    Publication date: May 3, 2018
    Inventor: Anand S. RAMALINGAM
  • Publication number: 20180122901
    Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 3, 2018
    Inventors: Seiyon KIM, Kelin J. KUHN, Tahir GHANI, Anand S. MURTHY, Mark ARMSTRONG, Rafael RIOS, Abhijit Jayant PETHE, Willy RACHMADY
  • Publication number: 20180115057
    Abstract: This document discloses one or more systems, apparatuses, methods, etc. for integrating coil antennas in a carbon fiber chassis portable device. More particularly, the carbon fiber chassis portable device containing unidirectional weave carbon fibers in its chassis—to support near field communications (NFC) related functions—is described.
    Type: Application
    Filed: July 6, 2017
    Publication date: April 26, 2018
    Inventors: Anand S. Konanur, Ulun Karacaoglu
  • Publication number: 20180108466
    Abstract: A Near Field Communications (NFC) antenna coil, having a first loop; and a second loop connected to the first loop to form a spiral shape, wherein the first loop and the second loop have different sizes to be mutually couplable with a first antenna pairing coil and a second antenna pairing coil, respectively.
    Type: Application
    Filed: October 25, 2017
    Publication date: April 19, 2018
    Applicant: Intel Corporation
    Inventors: Anand S. Konanur, Ulun Karacaoglu, Songnan Yang
  • Publication number: 20180108750
    Abstract: Techniques are disclosed for forming transistors on the same substrate with varied channel materials. The techniques include forming a replacement material region in the substrate, such region used to form a plurality of fins therefrom, the fins used to form transistor channel regions. In an example case, the substrate may comprise Si and the replacement materials may include Ge, SiGe, and/or at least one III-V material. The replacement material regions can have a width sufficient to ensure a substantially planar interface between the replacement material and the substrate material. Therefore, the fins formed from the replacement material regions can also have a substantially planar interface between the replacement material and the substrate material. One example benefit from being able to form replacement material channel regions with such substantially planar interfaces can include at least a 30 percent improvement in current flow at a fixed voltage.
    Type: Application
    Filed: June 12, 2015
    Publication date: April 19, 2018
    Applicant: INTEL CORPORATION
    Inventors: GLENN A. GLASS, ANAND S. MURTHY, HEI KAM, TAHIR GHANI, KARTHIK JAMBUNATHAN, CHANDRA S. MOHAPATRA
  • Patent number: 9940203
    Abstract: A cloud gateway (GW) device receives a first request for incremental backup from a client device over a LAN, where the first request includes a first file representing a difference between the incremental backup in view of a prior backup. In response, the cloud GW identifies a first base backup previously backed up to a cloud storage server over a WAN. A second request is transmitted to the cloud storage server over the WAN to copy the first base backup into a second base backup. A third request is transmitted to the cloud storage server over the WAN to replace a second file within the second base backup. The third request includes a second backup ID, a descriptor describing the file to be replaced, and content of the file received from the client without modifying the first file.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: April 10, 2018
    Assignee: EMC IP Holding Company LLC
    Inventors: Anand S. Ghatnekar, Kedar S. Patwardhan
  • Publication number: 20180098182
    Abstract: Communication devices and techniques for facilitating dual-mode communication within a single wireless communication device are described. In one embodiment, for example, an apparatus may include at least one memory and logic for a wireless communication device, at least a portion of the logic comprised in hardware coupled to the at least one memory, the logic to perform a transmission determination to determine whether to transmit a signal in a low-energy mode or a body-communication mode, map the signal to a body-communication channel responsive to the transmission determination indicating the body-communication mode, and map the signal to a low-energy channel responsive to the transmission determination indicating the low-energy mode. Other embodiments are described and claimed.
    Type: Application
    Filed: October 1, 2016
    Publication date: April 5, 2018
    Applicant: INTEL CORPORATION
    Inventors: JAROSLAW J. SYDIR, ANAND S. KONANUR, TIMOTHY F. COX
  • Patent number: 9934895
    Abstract: This document discloses one or more systems, apparatuses, methods, etc. for integrating a spiral near field communications (NFC) coil antenna to a portable device for consistent coupling with different tags and devices.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Anand S. Konanur, Ulun Karacaoglu, Songnan Yang
  • Patent number: 9935691
    Abstract: Described herein are architectures, platforms and methods for dynamic re-distribution of magnetic fields in a device during near field communication (NFC) related functions or transactions and/or wireless charging.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: April 3, 2018
    Assignee: Intel Corporation
    Inventors: Anand S. Konanur, Songnan Yang, Kwan Ho Lee, Ulun Karacaoglu, Farid Adrangi
  • Publication number: 20180089081
    Abstract: Technologies for providing cross data storage device communication include a compute device to transmit, with a processor, a move request to a first data storage device. The first data storage device is to transmit, in response to the move request, a completion notification to the processor. Additionally, the compute device is to read, with the first data storage device, after transmitting the completion notification, a block of data from a first non-volatile memory of the first data storage device to a volatile memory of the compute device. The first data storage device is to transmit to the second data storage device a second move request to move the block of data. The second data storage device is to write the block of data from the volatile memory to a second non-volatile memory of the second data storage device.
    Type: Application
    Filed: September 27, 2016
    Publication date: March 29, 2018
    Inventor: Anand S. Ramalingam
  • Publication number: 20180089076
    Abstract: Technologies for combining logical-to-physical address updates include a data storage device. The data storage device includes a non-volatile memory to store data and a logical to physical (L2P) table indicative of logical addresses and associated physical addresses of the data. Additionally, the data storage device includes a volatile memory to store one or more bins. Each bin is indicative of a subset of entries in the L2P table. Further, the data storage device includes a controller to allocate a bin in the volatile memory, write a plurality of updates to a subset of entries of the L2P table to the bin, and write the bin to the L2P table in a single write operation. Other embodiments are also described and claimed.
    Type: Application
    Filed: September 28, 2016
    Publication date: March 29, 2018
    Inventors: Peng Li, Anand S. Ramalingam, William K. Lui, Sanjeev N. Trika
  • Publication number: 20180088823
    Abstract: Systems, apparatuses and methods may provide for initiating an erase of a block of non-volatile memory in response to an erase command, wherein the block includes a plurality of sub-blocks. Additionally, a failure of the erase with respect to a first subset of the plurality of sub-blocks may be tracked on an individual sub-block basis, wherein the erase is successful with respect to a second subset of the plurality of sub-blocks. In one example, use of the second subset of the plurality of sub-blocks is permitted, whereas use of the first subset of the plurality of sub-blocks is prevented.
    Type: Application
    Filed: September 29, 2016
    Publication date: March 29, 2018
    Inventors: Anand S. Ramalingam, Jawad B. Khan, Pranav Kalavade
  • Publication number: 20180088810
    Abstract: A machine readable storage medium containing program code that when processed by a processor causes a method to be performed a method is described. The method includes executing a wear leveling routine by servicing cold data from a first queue in a non volatile storage device to write the cold data. The method also includes executing a garbage collection routing by servicing valid data from a second queue in the non volatile storage device to write the valid data. The method also includes servicing host write data from a third queue in the non volatile storage device to write the host write data wherein the first queue remains fixed and is serviced at a constant rate so that a runtime size of the third queue is not substantially affected by the wear leveling routine.
    Type: Application
    Filed: September 26, 2016
    Publication date: March 29, 2018
    Inventor: Anand S. RAMALINGAM
  • Patent number: 9929273
    Abstract: An embodiment includes a microelectronic device comprising: a substrate comprising a raised portion and a non-raised portion, wherein a dielectric material is disposed adjacent the raised portion, an epitaxial sub-fin structure disposed on the raised portion, wherein a bottom portion of the epitaxial sub-fin structure comprises an asymmetric profile, and an epitaxial fin device structure disposed on the sub-fin structure. Other embodiments are described herein.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: March 27, 2018
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Matthew V. Metz, Chandra S. Mohapatra, Gilbert Dewey, Nadia M. Rahhal-Orabi, Tahir Ghani, Anand S. Murthy, Jack T. Kavalieros, Glenn A. Glass
  • Patent number: 9923891
    Abstract: Systems, apparatuses, and methods may include a human body communication data storage device having at least first and second electrodes and a human body communication modem. A storage component communicating with the human body communication modem includes a first secure storage location provided with a user-specific authentication record and a second data storage location.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: March 20, 2018
    Assignee: Intel Corporation
    Inventors: Jaroslaw J. Sydir, Anand S. Konanur, Ulun Karacaoglu, Anthony G. LaMarca, Stephen R. Wood, Jeremy Burr
  • Patent number: 9922619
    Abstract: Disclosed herein is a computing device configured to send display data to a display through a near-field communication (NFC) interface. The computing device includes a chassis, a primary display, and a near-field communication interface to transmit display data to a secondary display.
    Type: Grant
    Filed: March 26, 2015
    Date of Patent: March 20, 2018
    Assignee: Intel Corporation
    Inventors: Anand S. Konanur, Ulun Karacaoglu, Justin M. Huttula, Farid Adrangi
  • Publication number: 20180064327
    Abstract: Embodiments of the present disclosure disclose a method and a computing unit for imaging of wider angle fundus of an eye of a subject. The method discloses guiding placement of an imaging device at set of predetermined locations on the eye. The method further comprises receiving set of images of the fundus of the eye upon determining the imaging device to be at least one of the set of predetermined locations, wherein the set of images are captured by the imaging device upon receiving instructions from the computing unit. The method further comprises determining quality of the set of images and concatenating the one or more images to provide a wider angle target image of the fundus of the eye.
    Type: Application
    Filed: May 19, 2015
    Publication date: March 8, 2018
    Inventors: Mahabaleswara Ram BHATT, Shyam Vasudeva RAO, Poston TIMOTHY, Anand S. VINEKAR
  • Patent number: 9893149
    Abstract: Techniques are disclosed for incorporating high mobility strained channels into fin-based transistors (e.g., FinFETs such as double-gate, trigate, etc), wherein a stress material is cladded onto the channel area of the fin. In one example embodiment, silicon germanium (SiGe) is cladded onto silicon fins to provide a desired stress, although other fin and cladding materials can be used. The techniques are compatible with typical process flows, and the cladding deposition can occur at a plurality of locations within the process flow. In some cases, the built-in stress from the cladding layer may be enhanced with a source/drain stressor that compresses both the fin and cladding layers in the channel. In some cases, an optional capping layer can be provided to improve the gate dielectric/semiconductor interface. In one such embodiment, silicon is provided over a SiGe cladding layer to improve the gate dielectric/semiconductor interface.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: February 13, 2018
    Assignee: INTEL CORPORATION
    Inventors: Stephen M. Cea, Anand S. Murthy, Glenn A. Glass, Daniel B. Aubertine, Tahir Ghani, Jack T. Kavalieros, Roza Kotlyar
  • Publication number: 20180035879
    Abstract: Embodiments of the present disclosure provides an illumination device (300), comprises of one or more sources (301) which provides light arranged in a predefined configuration and a collar (303) with a first end (304) and a second end (305) to guide light received at the first end towards the second end. The collar guides the light in a medium between an internal wall and an external wall of the collar by reflection. The light from the second end is used to illuminate a target area for an imaging device. The method of illuminating a target area by an illumination device comprises of powering one or more sources to provide light for illumination and guiding the light in the medium to illuminate on the target area.
    Type: Application
    Filed: June 4, 2015
    Publication date: February 8, 2018
    Inventors: Cothuru Santosh Kumar, Shyam Vasudeva Rao, Timothy Poston, Anand S. Vinekar
  • Patent number: 9882009
    Abstract: Techniques are disclosed for using a high resistance layer between a III-V channel layer and a group IV substrate for semiconducting devices, such as metal-oxide-semiconductor (MOS) transistors. The high resistance layer can be used to minimize (or eliminate) current flow from source to drain that follows a path other than directly through the channel. In some cases, the high resistance layer may be a III-V wide bandgap layer. In some such cases, the wide bandgap layer may have a bandgap greater than 1.4 electron volts (eV), and may even have a bandgap greater than 2.0 eV. In other cases, the wide bandgap layer may be partially or completely converted to an insulator through oxidation or nitridation, for example. The resulting structures may be used with planar, finned, or nanowire/nanoribbon transistor architectures to help prevent substrate leakage problems.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: January 30, 2018
    Assignee: INTEL CORPORATION
    Inventors: Glenn A. Glass, Anand S. Murthy